#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_asym_dev_private;
struct qat_comp_dev_private;
struct qat_pci_device {
struct qat_sym_dev_private *sym_dev;
/**< link back to cryptodev private data */
struct rte_device sym_rte_dev;
- /**< This represents the crypto subset of this pci device.
+ /**< This represents the crypto sym subset of this pci device.
+ * Register with this rather than with the one in
+ * pci_dev so that its driver can have a crypto-specific name
+ */
+
+ /* Data relating to asymmetric crypto service */
+ struct qat_asym_dev_private *asym_dev;
+ /**< link back to cryptodev private data */
+ struct rte_device asym_rte_dev;
+ /**< This represents the crypto asym subset of this pci device.
* Register with this rather than with the one in
* pci_dev so that its driver can have a crypto-specific name
*/
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];