uint16_t val;
};
-enum qat_comp_num_im_buffers {
- QAT_NUM_INTERM_BUFS_GEN1 = 12,
- QAT_NUM_INTERM_BUFS_GEN2 = 20,
- QAT_NUM_INTERM_BUFS_GEN3 = 64
-};
-
struct qat_device_info {
const struct rte_memzone *mz;
/**< mz to store the qat_pci_device so it can be
extern struct qat_device_info qat_pci_devs[];
-struct qat_sym_dev_private;
-struct qat_asym_dev_private;
+struct qat_cryptodev_private;
struct qat_comp_dev_private;
/*
/**< links to qps set up for each service, index same as on API */
/* Data relating to symmetric crypto service */
- struct qat_sym_dev_private *sym_dev;
+ struct qat_cryptodev_private *sym_dev;
/**< link back to cryptodev private data */
int qat_sym_driver_id;
/**< Symmetric driver id used by this device */
/* Data relating to asymmetric crypto service */
- struct qat_asym_dev_private *asym_dev;
+ struct qat_cryptodev_private *asym_dev;
/**< link back to cryptodev private data */
int qat_asym_driver_id;
/* Data relating to compression service */
struct qat_comp_dev_private *comp_dev;
/**< link back to compressdev private data */
- struct qat_qp_hw_data qp_gen4_data[QAT_GEN4_BUNDLE_NUM]
- [QAT_GEN4_QPS_PER_BUNDLE_NUM];
- /**< Data of ring configuration on gen4 */
void *misc_bar_io_addr;
/**< Address of misc bar */
void *dev_private;
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
- enum qat_comp_num_im_buffers comp_num_im_bufs_required;
struct qat_pf2vf_dev *pf2vf_dev;
};