net/mlx5: add flow flush

[dpdk.git] / drivers / common / qat / qat_qp.h

diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 726cd2e..66f0094 100644 (file)
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018 Intel Corporation
+ * Copyright(c) 2018-2022 Intel Corporation
  */
 #ifndef _QAT_QP_H_
 #define _QAT_QP_H_
@@ -12,16 +12,6 @@
 
 #define QAT_QP_MIN_INFL_THRESHOLD      256
 
-/* Default qp configuration for GEN4 devices */
-#define QAT_GEN4_QP_DEFCON     (QAT_SERVICE_SYMMETRIC |        \
-                               QAT_SERVICE_SYMMETRIC << 8 |    \
-                               QAT_SERVICE_SYMMETRIC << 16 |   \
-                               QAT_SERVICE_SYMMETRIC << 24)
-
-/* QAT GEN 4 specific macros */
-#define QAT_GEN4_BUNDLE_NUM             4
-#define QAT_GEN4_QPS_PER_BUNDLE_NUM     1
-
 struct qat_pci_device;
 
 /**
@@ -46,6 +36,51 @@ struct qat_queue {
        /* number of responses processed since last CSR head write */
 };
 
+/**
+ * Type define qat_op_build_request_t function pointer, passed in as argument
+ * in enqueue op burst, where a build request assigned base on the type of
+ * crypto op.
+ *
+ * @param in_op
+ *    An input op pointer
+ * @param out_msg
+ *    out_meg pointer
+ * @param op_cookie
+ *    op cookie pointer
+ * @param opaque
+ *    an opaque data may be used to store context may be useful between
+ *    2 enqueue operations.
+ * @param dev_gen
+ *    qat device gen id
+ * @return
+ *   - 0 if the crypto request is build successfully,
+ *   - EINVAL if error
+ **/
+typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg,
+               void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen);
+
+/**
+ * Type define qat_op_dequeue_t function pointer, passed in as argument
+ * in dequeue op burst, where a dequeue op assigned base on the type of
+ * crypto op.
+ *
+ * @param op
+ *    An input op pointer
+ * @param resp
+ *    qat response msg pointer
+ * @param op_cookie
+ *    op cookie pointer
+ * @param dequeue_err_count
+ *    dequeue error counter
+ * @return
+ *    - 0 if dequeue OP is successful
+ *    - EINVAL if error
+ **/
+typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie,
+               uint64_t *dequeue_err_count __rte_unused);
+
+#define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE      2
+
 struct qat_qp {
        void                    *mmap_bar_addr;
        struct qat_queue        tx_q;
@@ -54,6 +89,7 @@ struct qat_qp {
        struct rte_mempool *op_cookie_pool;
        void **op_cookies;
        uint32_t nb_descriptors;
+       uint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE];
        enum qat_device_gen qat_dev_gen;
        enum qat_service_type service_type;
        struct qat_pci_device *qat_dev;
@@ -88,13 +124,15 @@ struct qat_qp_config {
 };
 
 uint16_t
-qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
+qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,
+               void **ops, uint16_t nb_ops);
 
 uint16_t
 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);
 
 uint16_t
-qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
+qat_dequeue_op_burst(void *qp, void **ops,
+               qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops);
 
 int
 qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr);
@@ -106,7 +144,11 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
 
 int
 qat_qps_per_service(struct qat_pci_device *qat_dev,
-                       enum qat_service_type service);
+               enum qat_service_type service);
+
+const struct qat_qp_hw_data *
+qat_qp_get_hw_data(struct qat_pci_device *qat_dev,
+               enum qat_service_type service, uint16_t qp_id);
 
 int
 qat_cq_get_fw_version(struct qat_qp *qp);
@@ -116,11 +158,6 @@ int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
                          void *op_cookie __rte_unused,
                          uint64_t *dequeue_err_count __rte_unused);
-
-int
-qat_select_valid_queue(struct qat_pci_device *qat_dev, int qp_id,
-                       enum qat_service_type service_type);
-
 int
 qat_read_qp_config(struct qat_pci_device *qat_dev);
 
@@ -166,7 +203,4 @@ struct qat_qp_hw_spec_funcs {
 
 extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
 
-extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
-extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
-
 #endif /* _QAT_QP_H_ */