net/mlx5: fix DevX CQ attributes values

[dpdk.git] / drivers / common / qat / qat_qp.h

diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 980c2ba..74f7e7d 100644 (file)
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -11,15 +11,8 @@ struct qat_pci_device;
 
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
-#define QAT_CSR_TAIL_WRITE_THRESH 32U
-/* number of requests to accumulate before writing tail CSR */
-#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
-/* number of inflights below which no tail write coalescing should occur */
 
-typedef int (*build_request_t)(void *op,
-               uint8_t *req, void *op_cookie,
-               enum qat_device_gen qat_dev_gen);
-/**< Build a request from an op. */
+#define QAT_QP_MIN_INFL_THRESHOLD      256
 
 /**
  * Structure with data needed for creation of queue pair.
@@ -32,6 +25,7 @@ struct qat_qp_hw_data {
        uint16_t tx_msg_size;
        uint16_t rx_msg_size;
 };
+
 /**
  * Structure with data needed for creation of queue pair.
  */
@@ -40,7 +34,6 @@ struct qat_qp_config {
        uint32_t nb_descriptors;
        uint32_t cookie_size;
        int socket_id;
-       build_request_t build_request;
        const char *service_str;
 };
 
@@ -55,8 +48,8 @@ struct qat_queue {
        uint32_t        tail;                   /* Shadow copy of the tail */
        uint32_t        modulo_mask;
        uint32_t        msg_size;
-       uint16_t        max_inflights;
        uint32_t        queue_size;
+       uint8_t         trailz;
        uint8_t         hw_bundle_number;
        uint8_t         hw_queue_number;
        /* HW queue aka ring offset on bundle */
@@ -64,13 +57,10 @@ struct qat_queue {
        uint32_t        csr_tail;               /* last written tail value */
        uint16_t        nb_processed_responses;
        /* number of responses processed since last CSR head write */
-       uint16_t        nb_pending_requests;
-       /* number of requests pending since last CSR tail write */
 };
 
 struct qat_qp {
        void                    *mmap_bar_addr;
-       uint16_t                inflights16;
        struct qat_queue        tx_q;
        struct qat_queue        rx_q;
        struct qat_common_stats stats;
@@ -78,10 +68,13 @@ struct qat_qp {
        void **op_cookies;
        uint32_t nb_descriptors;
        enum qat_device_gen qat_dev_gen;
-       build_request_t build_request;
        enum qat_service_type service_type;
        struct qat_pci_device *qat_dev;
        /**< qat device this qp is on */
+       uint32_t enqueued;
+       uint32_t dequeued __rte_aligned(4);
+       uint16_t max_inflights;
+       uint16_t min_enq_burst_threshold;
 } __rte_cache_aligned;
 
 extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
@@ -90,6 +83,9 @@ extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
 uint16_t
 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
 
+uint16_t
+qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);
+
 uint16_t
 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
 
@@ -105,6 +101,9 @@ int
 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
                        enum qat_service_type service);
 
+int
+qat_cq_get_fw_version(struct qat_qp *qp);
+
 /* Needed for weak function*/
 int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,