EFX_FAMILY_HUNTINGTON,
EFX_FAMILY_MEDFORD,
EFX_FAMILY_MEDFORD2,
+ EFX_FAMILY_RIVERHEAD,
EFX_FAMILY_NTYPES
} efx_family_t;
#define EFX_PCI_VENID_SFC 0x1924
+#define EFX_PCI_VENID_XILINX 0x10EE
#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
+#define EFX_PCI_DEVID_RIVERHEAD 0x0100
+#define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
#define EFX_MEM_BAR_SIENA 2
#define EFX_MEM_BAR_MEDFORD2 0
+/* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
+#define EFX_MEM_BAR_RIVERHEAD 2
+
/* Error codes */
#if EFSYS_OPT_MCDI
-#if EFX_OPTS_EF10()
-/* EF10 architecture NICs require MCDIv2 commands */
+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
+/* EF10 architecture and Riverhead NICs require MCDIv2 commands */
#define WITH_MCDI_V2 1
#endif
#if EFSYS_OPT_BIST
uint32_t enc_bist_mask;
#endif /* EFSYS_OPT_BIST */
-#if EFX_OPTS_EF10()
+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
uint32_t enc_pf;
uint32_t enc_vf;
uint32_t enc_privilege_mask;
-#endif /* EFX_OPTS_EF10() */
+#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
+ boolean_t enc_evq_init_done_ev_supported;
boolean_t enc_bug26807_workaround;
boolean_t enc_bug35388_workaround;
boolean_t enc_bug41750_workaround;
#endif /* EFSYS_OPT_EV_PREFETCH */
+LIBEFX_API
+extern void
+efx_ev_qcreate_check_init_done(
+ __in efx_evq_t *eep,
+ __in const efx_ev_callbacks_t *eecp,
+ __in_opt void *arg);
+
LIBEFX_API
extern void
efx_ev_qpoll(