#if EFSYS_OPT_TUNNEL
typedef struct efx_tunnel_ops_s {
- boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
efx_rc_t (*eto_reconfigure)(efx_nic_t *);
+ void (*eto_fini)(efx_nic_t *);
} efx_tunnel_ops_t;
#endif /* EFSYS_OPT_TUNNEL */
#if EFSYS_OPT_TUNNEL
+/* State of a UDP tunnel table entry */
+typedef enum efx_tunnel_udp_entry_state_e {
+ EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */
+ EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */
+ EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */
+} efx_tunnel_udp_entry_state_t;
+
+#if EFSYS_OPT_RIVERHEAD
+typedef uint32_t efx_vnic_encap_rule_handle_t;
+#endif /* EFSYS_OPT_RIVERHEAD */
+
typedef struct efx_tunnel_udp_entry_s {
uint16_t etue_port; /* host/cpu-endian */
uint16_t etue_protocol;
+ boolean_t etue_busy;
+ efx_tunnel_udp_entry_state_t etue_state;
+#if EFSYS_OPT_RIVERHEAD
+ efx_vnic_encap_rule_handle_t etue_handle;
+#endif /* EFSYS_OPT_RIVERHEAD */
} efx_tunnel_udp_entry_t;
typedef struct efx_tunnel_cfg_s {
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+#if EFSYS_OPT_MAE
+
+typedef struct efx_mae_field_cap_s {
+ uint32_t emfc_support;
+ boolean_t emfc_mask_affects_class;
+ boolean_t emfc_match_affects_class;
+} efx_mae_field_cap_t;
+
+typedef struct efx_mae_s {
+ uint32_t em_max_n_action_prios;
+ /*
+ * The number of MAE field IDs recognised by the FW implementation.
+ * Any field ID greater than or equal to this value is unsupported.
+ */
+ uint32_t em_max_nfields;
+ /** Action rule match field capabilities. */
+ efx_mae_field_cap_t *em_action_rule_field_caps;
+ size_t em_action_rule_field_caps_size;
+ uint32_t em_max_n_outer_prios;
+ uint32_t em_encap_types_supported;
+} efx_mae_t;
+
+#endif /* EFSYS_OPT_MAE */
+
#define EFX_DRV_VER_MAX 20
typedef struct efx_drv_cfg_s {
#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
const efx_proxy_ops_t *en_epop;
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+#if EFSYS_OPT_MAE
+ efx_mae_t *en_maep;
+#endif /* EFSYS_OPT_MAE */
};
#define EFX_FAMILY_IS_EF10(_enp) \
typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
const efx_ev_callbacks_t *, void *);
+#if EFSYS_OPT_EV_EXTENDED_WIDTH
+typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *,
+ const efx_ev_callbacks_t *, void *);
+#endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */
+
typedef struct efx_evq_rxq_state_s {
unsigned int eers_rx_read_ptr;
unsigned int eers_rx_mask;
efx_ev_handler_t ee_mcdi;
#endif /* EFSYS_OPT_MCDI */
+#if EFSYS_OPT_DESC_PROXY
+ efx_ev_ew_handler_t ee_ew_txq_desc;
+ efx_ev_ew_handler_t ee_ew_virtq_desc;
+#endif /* EFSYS_OPT_DESC_PROXY */
+
efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
};
extern __checkReturn efx_rc_t
efx_pci_config_find_next_ext_cap(
__in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
__in uint16_t cap_id,
__inout size_t *offsetp);
extern __checkReturn efx_rc_t
efx_pci_config_next_ext_cap(
__in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
__inout size_t *offsetp);
/*
extern __checkReturn efx_rc_t
efx_pci_find_next_xilinx_cap_table(
__in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
__inout size_t *pci_cap_offsetp,
__out unsigned int *xilinx_tbl_barp,
__out efsys_dma_addr_t *xilinx_tbl_offsetp);
extern __checkReturn efx_rc_t
efx_pci_read_ext_cap_xilinx_table(
__in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
__in size_t cap_offset,
__out unsigned int *barp,
__out efsys_dma_addr_t *offsetp);
+/*
+ * Find a capability with specified format_id in a Xilinx capabilities table.
+ * Searching is started from provided offset, taking skip_first into account.
+ * If search succeeds, found capability is in modified offset.
+ *
+ * Returns ENOENT if an entry with specified format id is not found.
+ */
+LIBEFX_INTERNAL
+extern __checkReturn efx_rc_t
+efx_pci_xilinx_cap_tbl_find(
+ __in efsys_bar_t *esbp,
+ __in uint32_t format_id,
+ __in boolean_t skip_first,
+ __inout efsys_dma_addr_t *entry_offsetp);
+
#endif /* EFSYS_OPT_PCI */
+#if EFSYS_OPT_MAE
+
+struct efx_mae_match_spec_s {
+ efx_mae_rule_type_t emms_type;
+ uint32_t emms_prio;
+ union emms_mask_value_pairs {
+ uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
+ } emms_mask_value_pairs;
+};
+
+typedef enum efx_mae_action_e {
+ /* These actions are strictly ordered. */
+ EFX_MAE_ACTION_VLAN_POP,
+ EFX_MAE_ACTION_VLAN_PUSH,
+
+ /*
+ * These actions are not strictly ordered and can
+ * be passed by a client in any order (before DELIVER).
+ * However, these enumerants must be kept compactly
+ * in the end of the enumeration (before DELIVER).
+ */
+ EFX_MAE_ACTION_FLAG,
+ EFX_MAE_ACTION_MARK,
+
+ /* DELIVER is always the last action. */
+ EFX_MAE_ACTION_DELIVER,
+
+ EFX_MAE_NACTIONS
+} efx_mae_action_t;
+
+/* MAE VLAN_POP action can handle 1 or 2 tags. */
+#define EFX_MAE_VLAN_POP_MAX_NTAGS (2)
+
+/* MAE VLAN_PUSH action can handle 1 or 2 tags. */
+#define EFX_MAE_VLAN_PUSH_MAX_NTAGS (2)
+
+typedef struct efx_mae_action_vlan_push_s {
+ uint16_t emavp_tpid_be;
+ uint16_t emavp_tci_be;
+} efx_mae_action_vlan_push_t;
+
+struct efx_mae_actions_s {
+ /* Bitmap of actions in spec, indexed by action type */
+ uint32_t ema_actions;
+
+ unsigned int ema_n_vlan_tags_to_pop;
+ unsigned int ema_n_vlan_tags_to_push;
+ efx_mae_action_vlan_push_t ema_vlan_push_descs[
+ EFX_MAE_VLAN_PUSH_MAX_NTAGS];
+ uint32_t ema_mark_value;
+ efx_mport_sel_t ema_deliver_mport;
+};
+
+#endif /* EFSYS_OPT_MAE */
+
#ifdef __cplusplus
}
#endif