#if EFSYS_OPT_TUNNEL
typedef struct efx_tunnel_ops_s {
- boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
efx_rc_t (*eto_reconfigure)(efx_nic_t *);
+ void (*eto_fini)(efx_nic_t *);
} efx_tunnel_ops_t;
#endif /* EFSYS_OPT_TUNNEL */
#if EFSYS_OPT_TUNNEL
+/* State of a UDP tunnel table entry */
+typedef enum efx_tunnel_udp_entry_state_e {
+ EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */
+ EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */
+ EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */
+} efx_tunnel_udp_entry_state_t;
+
+#if EFSYS_OPT_RIVERHEAD
+typedef uint32_t efx_vnic_encap_rule_handle_t;
+#endif /* EFSYS_OPT_RIVERHEAD */
+
typedef struct efx_tunnel_udp_entry_s {
uint16_t etue_port; /* host/cpu-endian */
uint16_t etue_protocol;
+ boolean_t etue_busy;
+ efx_tunnel_udp_entry_state_t etue_state;
+#if EFSYS_OPT_RIVERHEAD
+ efx_vnic_encap_rule_handle_t etue_handle;
+#endif /* EFSYS_OPT_RIVERHEAD */
} efx_tunnel_udp_entry_t;
typedef struct efx_tunnel_cfg_s {
int ena_vi_base;
int ena_vi_count;
int ena_vi_shift;
+ uint32_t ena_fcw_base;
#if EFSYS_OPT_VPD
caddr_t ena_svpd;
size_t ena_svpd_length;
* Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
* to ensure the correct runtime VI window size is used on Medford2.
*
+ * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control
+ * window registers, to ensure the correct starting offset is used.
+ *
* Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
*/
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
+/*
+ * Accessors for memory BAR function control window registers.
+ *
+ * The function control window is located at an offset which can be
+ * non-zero in case of Riverhead.
+ */
+
+#if EFSYS_OPT_RIVERHEAD
+
+#define EFX_BAR_FCW_READD(_enp, _reg, _edp) \
+ do { \
+ EFX_CHECK_REG((_enp), (_reg)); \
+ EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \
+ (_enp)->en_arch.ef10.ena_fcw_base, \
+ (_edp), B_FALSE); \
+ EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \
+ uint32_t, _reg ## _OFST, \
+ uint32_t, (_edp)->ed_u32[0]); \
+ _NOTE(CONSTANTCONDITION) \
+ } while (B_FALSE)
+
+#define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \
+ do { \
+ EFX_CHECK_REG((_enp), (_reg)); \
+ EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \
+ uint32_t, _reg ## _OFST, \
+ uint32_t, (_edp)->ed_u32[0]); \
+ EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \
+ (_enp)->en_arch.ef10.ena_fcw_base, \
+ (_edp), B_FALSE); \
+ _NOTE(CONSTANTCONDITION) \
+ } while (B_FALSE)
+
+#endif /* EFSYS_OPT_RIVERHEAD */
+
/*
* Accessors for memory BAR per-VI registers.
*
__in efx_nic_t *enp,
__in uint32_t instance);
+typedef struct efx_mcdi_init_rxq_params_s {
+ boolean_t disable_scatter;
+ boolean_t want_inner_classes;
+ uint32_t buf_size;
+ uint32_t ps_buf_size;
+ uint32_t es_bufs_per_desc;
+ uint32_t es_max_dma_len;
+ uint32_t es_buf_stride;
+ uint32_t hol_block_timeout;
+ uint32_t prefix_id;
+} efx_mcdi_init_rxq_params_t;
+
LIBEFX_INTERNAL
extern __checkReturn efx_rc_t
efx_mcdi_init_rxq(
__in uint32_t label,
__in uint32_t instance,
__in efsys_mem_t *esmp,
- __in boolean_t disable_scatter,
- __in boolean_t want_inner_classes,
- __in uint32_t buf_size,
- __in uint32_t ps_bufsize,
- __in uint32_t es_bufs_per_desc,
- __in uint32_t es_max_dma_len,
- __in uint32_t es_buf_stride,
- __in uint32_t hol_block_timeout);
+ __in const efx_mcdi_init_rxq_params_t *params);
LIBEFX_INTERNAL
extern __checkReturn efx_rc_t
#endif /* EFSYS_OPT_MAC_STATS */
+#if EFSYS_OPT_PCI
+
+/*
+ * Find the next extended capability in a PCI device's config space
+ * with specified capability id.
+ * Passing 0 offset makes the function search from the start.
+ * If search succeeds, found capability is in modified offset.
+ *
+ * Returns ENOENT if a capability is not found.
+ */
+LIBEFX_INTERNAL
+extern __checkReturn efx_rc_t
+efx_pci_config_find_next_ext_cap(
+ __in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
+ __in uint16_t cap_id,
+ __inout size_t *offsetp);
+
+/*
+ * Get the next extended capability in a PCI device's config space.
+ * Passing 0 offset makes the function get the first capability.
+ * If search succeeds, the capability is in modified offset.
+ *
+ * Returns ENOENT if there is no next capability.
+ */
+LIBEFX_INTERNAL
+extern __checkReturn efx_rc_t
+efx_pci_config_next_ext_cap(
+ __in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
+ __inout size_t *offsetp);
+
+/*
+ * Find the next Xilinx capabilities table location by searching
+ * PCI extended capabilities.
+ *
+ * Returns ENOENT if a table location is not found.
+ */
+LIBEFX_INTERNAL
+extern __checkReturn efx_rc_t
+efx_pci_find_next_xilinx_cap_table(
+ __in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
+ __inout size_t *pci_cap_offsetp,
+ __out unsigned int *xilinx_tbl_barp,
+ __out efsys_dma_addr_t *xilinx_tbl_offsetp);
+
+/*
+ * Read a Xilinx extended PCI capability that gives the location
+ * of a Xilinx capabilities table.
+ *
+ * Returns ENOENT if the extended PCI capability does not contain
+ * Xilinx capabilities table locator.
+ */
+LIBEFX_INTERNAL
+extern __checkReturn efx_rc_t
+efx_pci_read_ext_cap_xilinx_table(
+ __in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
+ __in size_t cap_offset,
+ __out unsigned int *barp,
+ __out efsys_dma_addr_t *offsetp);
+
+/*
+ * Find a capability with specified format_id in a Xilinx capabilities table.
+ * Searching is started from provided offset, taking skip_first into account.
+ * If search succeeds, found capability is in modified offset.
+ *
+ * Returns ENOENT if an entry with specified format id is not found.
+ */
+LIBEFX_INTERNAL
+extern __checkReturn efx_rc_t
+efx_pci_xilinx_cap_tbl_find(
+ __in efsys_bar_t *esbp,
+ __in uint32_t format_id,
+ __in boolean_t skip_first,
+ __inout efsys_dma_addr_t *entry_offsetp);
+
+#endif /* EFSYS_OPT_PCI */
+
#ifdef __cplusplus
}
#endif
git.droids-corp.org / dpdk.git / blobdiff