/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- * All rights reserved.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
*/
#include "efx.h"
return (rc);
}
+static __checkReturn efx_rc_t
+efx_mae_get_outer_rule_caps(
+ __in efx_nic_t *enp,
+ __in unsigned int field_ncaps,
+ __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
+{
+ efx_mcdi_req_t req;
+ EFX_MCDI_DECLARE_BUF(payload,
+ MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
+ MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
+ unsigned int mcdi_field_ncaps;
+ unsigned int i;
+ efx_rc_t rc;
+
+ if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
+ MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail2;
+ }
+
+ mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
+
+ if (req.emr_out_length_used <
+ MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
+ rc = EMSGSIZE;
+ goto fail3;
+ }
+
+ if (mcdi_field_ncaps > field_ncaps) {
+ rc = EMSGSIZE;
+ goto fail4;
+ }
+
+ for (i = 0; i < mcdi_field_ncaps; ++i) {
+ uint32_t match_flag;
+ uint32_t mask_flag;
+
+ field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
+ MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
+ MAE_FIELD_FLAGS_SUPPORT_STATUS);
+
+ match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
+ MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
+ MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
+
+ field_caps[i].emfc_match_affects_class =
+ (match_flag != 0) ? B_TRUE : B_FALSE;
+
+ mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
+ MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
+ MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
+
+ field_caps[i].emfc_mask_affects_class =
+ (mask_flag != 0) ? B_TRUE : B_FALSE;
+ }
+
+ return (0);
+
+fail4:
+ EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
static __checkReturn efx_rc_t
efx_mae_get_action_rule_caps(
__in efx_nic_t *enp,
__in efx_nic_t *enp)
{
const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
+ efx_mae_field_cap_t *or_fcaps;
+ size_t or_fcaps_size;
efx_mae_field_cap_t *ar_fcaps;
size_t ar_fcaps_size;
efx_mae_t *maep;
if (rc != 0)
goto fail3;
+ or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
+ EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
+ if (or_fcaps == NULL) {
+ rc = ENOMEM;
+ goto fail4;
+ }
+
+ maep->em_outer_rule_field_caps_size = or_fcaps_size;
+ maep->em_outer_rule_field_caps = or_fcaps;
+
+ rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
+ if (rc != 0)
+ goto fail5;
+
ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
if (ar_fcaps == NULL) {
rc = ENOMEM;
- goto fail4;
+ goto fail6;
}
maep->em_action_rule_field_caps_size = ar_fcaps_size;
rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
if (rc != 0)
- goto fail5;
+ goto fail7;
return (0);
-fail5:
+fail7:
EFSYS_PROBE(fail5);
EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
+fail6:
+ EFSYS_PROBE(fail4);
+fail5:
+ EFSYS_PROBE(fail5);
+ EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
maep->em_action_rule_field_caps);
+ EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
+ maep->em_outer_rule_field_caps);
EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
enp->en_maep = NULL;
}
efx_rc_t rc;
switch (type) {
+ case EFX_MAE_RULE_OUTER:
+ break;
case EFX_MAE_RULE_ACTION:
break;
default:
EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
+ EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
+ EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
+ EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
+ EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
+ EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
+ EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
+ EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
+ EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
+ EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
+ EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
+ EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
+ EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
+ EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
+ EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
+ EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
+ EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
+ EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
+ EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
EFX_MAE_FIELD_CAP_NIDS
} efx_mae_field_cap_id_t;
* The information in it is meant to be used internally by
* APIs for addressing a given field in a mask-value pairs
* structure and for validation purposes.
+ *
+ * A field may have an alternative one. This structure
+ * has additional members to reference the alternative
+ * field's mask. See efx_mae_match_spec_is_valid().
*/
typedef struct efx_mae_mv_desc_s {
efx_mae_field_cap_id_t emmd_field_cap_id;
size_t emmd_mask_size;
size_t emmd_mask_offset;
+ /*
+ * Having the alternative field's mask size set to 0
+ * means that there's no alternative field specified.
+ */
+ size_t emmd_alt_mask_size;
+ size_t emmd_alt_mask_offset;
+
+ /* Primary field and the alternative one are of the same endianness. */
efx_mae_field_endianness_t emmd_endianness;
} efx_mae_mv_desc_t;
MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
+ 0, 0 /* no alternative field */, \
_endianness \
}
EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
+#undef EFX_MAE_MV_DESC
+};
+
+/* Indices to this array are provided by efx_mae_field_id_t */
+static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
+#define EFX_MAE_MV_DESC(_name, _endianness) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
+ 0, 0 /* no alternative field */, \
+ _endianness \
+ }
+
+/* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
+#define EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN, \
+ MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST, \
+ _endianness \
+ }
+
+ EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
+ EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
+ EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
+
+#undef EFX_MAE_MV_DESC_ALT
#undef EFX_MAE_MV_DESC
};
MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
memset(mportp, 0, sizeof (*mportp));
- mportp->sel = dword.ed_u32[0];
+ /*
+ * The constructed DWORD is little-endian,
+ * but the resulting value is meant to be
+ * passed to MCDIs, where it will undergo
+ * host-order to little endian conversion.
+ */
+ mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
return (0);
MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
memset(mportp, 0, sizeof (*mportp));
- mportp->sel = dword.ed_u32[0];
+ /*
+ * The constructed DWORD is little-endian,
+ * but the resulting value is meant to be
+ * passed to MCDIs, where it will undergo
+ * host-order to little endian conversion.
+ */
+ mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
return (0);
__in_bcount(mask_size) const uint8_t *mask)
{
const efx_mae_mv_desc_t *descp;
+ unsigned int desc_set_nentries;
uint8_t *mvp;
efx_rc_t rc;
- if (field_id >= EFX_MAE_FIELD_NIDS) {
- rc = EINVAL;
- goto fail1;
- }
-
switch (spec->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.outer;
+ break;
case EFX_MAE_RULE_ACTION:
+ desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
descp = &__efx_mae_action_rule_mv_desc_set[field_id];
mvp = spec->emms_mask_value_pairs.action;
break;
default:
rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if ((unsigned int)field_id >= desc_set_nentries) {
+ rc = EINVAL;
goto fail2;
}
- if (value_size != descp->emmd_value_size) {
+ if (descp->emmd_mask_size == 0) {
+ /* The ID points to a gap in the array of field descriptors. */
rc = EINVAL;
goto fail3;
}
- if (mask_size != descp->emmd_mask_size) {
+ if (value_size != descp->emmd_value_size) {
rc = EINVAL;
goto fail4;
}
+ if (mask_size != descp->emmd_mask_size) {
+ rc = EINVAL;
+ goto fail5;
+ }
+
if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
+ unsigned int i;
+
/*
* The mask/value are in network (big endian) order.
* The MCDI request field is also big endian.
*/
- memcpy(mvp + descp->emmd_value_offset, value, value_size);
- memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
+
+ EFSYS_ASSERT3U(value_size, ==, mask_size);
+
+ for (i = 0; i < value_size; ++i) {
+ uint8_t *v_bytep = mvp + descp->emmd_value_offset + i;
+ uint8_t *m_bytep = mvp + descp->emmd_mask_offset + i;
+
+ /*
+ * Apply the mask (which may be all-zeros) to the value.
+ *
+ * If this API is provided with some value to set for a
+ * given field in one specification and with some other
+ * value to set for this field in another specification,
+ * then, if the two masks are all-zeros, the field will
+ * avoid being counted as a mismatch when comparing the
+ * specifications using efx_mae_match_specs_equal() API.
+ */
+ *v_bytep = value[i] & mask[i];
+ *m_bytep = mask[i];
+ }
} else {
efx_dword_t dword;
return (0);
+fail5:
+ EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
fail3:
return (rc);
}
+ __checkReturn boolean_t
+efx_mae_match_specs_equal(
+ __in const efx_mae_match_spec_t *left,
+ __in const efx_mae_match_spec_t *right)
+{
+ return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
+}
+
#define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
((_mask)[(_bit) / (_mask_page_nbits)] & \
(1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
-static inline boolean_t
+static boolean_t
efx_mask_is_prefix(
__in size_t mask_nbytes,
__in_bcount(mask_nbytes) const uint8_t *maskp)
return B_TRUE;
}
-static inline boolean_t
+static boolean_t
efx_mask_is_all_ones(
__in size_t mask_nbytes,
__in_bcount(mask_nbytes) const uint8_t *maskp)
return (t == (uint8_t)(~0));
}
-static inline boolean_t
+static boolean_t
efx_mask_is_all_zeros(
__in size_t mask_nbytes,
__in_bcount(mask_nbytes) const uint8_t *maskp)
const uint8_t *mvp;
switch (spec->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ field_caps = maep->em_outer_rule_field_caps;
+ desc_setp = __efx_mae_outer_rule_mv_desc_set;
+ desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ mvp = spec->emms_mask_value_pairs.outer;
+ break;
case EFX_MAE_RULE_ACTION:
field_caps = maep->em_action_rule_field_caps;
desc_setp = __efx_mae_action_rule_mv_desc_set;
if (field_caps == NULL)
return (B_FALSE);
- for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
+ for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
+ ++field_id) {
const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
+ const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
+ size_t alt_m_size = descp->emmd_alt_mask_size;
size_t m_size = descp->emmd_mask_size;
if (m_size == 0)
continue; /* Skip array gap */
- if (field_cap_id >= field_ncaps)
- break;
+ if ((unsigned int)field_cap_id >= field_ncaps) {
+ /*
+ * The FW has not reported capability status for
+ * this field. Make sure that its mask is zeroed.
+ */
+ is_valid = efx_mask_is_all_zeros(m_size, m_buf);
+ if (is_valid != B_FALSE)
+ continue;
+ else
+ break;
+ }
switch (field_caps[field_cap_id].emfc_support) {
case MAE_FIELD_SUPPORTED_MATCH_MASK:
break;
case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
is_valid = efx_mask_is_all_ones(m_size, m_buf);
+
+ if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
+ /*
+ * This field has an alternative one. The FW
+ * reports ALWAYS for both implying that one
+ * of them is required to have all-ones mask.
+ *
+ * The primary field's mask is incorrect; go
+ * on to check that of the alternative field.
+ */
+ is_valid = efx_mask_is_all_ones(alt_m_size,
+ alt_m_buf);
+ }
break;
case MAE_FIELD_SUPPORTED_MATCH_NEVER:
case MAE_FIELD_UNSUPPORTED:
EFX_POPULATE_DWORD_1(dword,
MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
- mport.sel = dword.ed_u32[0];
+ /*
+ * The constructed DWORD is little-endian,
+ * but the resulting value is meant to be
+ * passed to MCDIs, where it will undergo
+ * host-order to little endian conversion.
+ */
+ mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
arg = (const uint8_t *)&mport.sel;
efx_rc_t rc;
switch (left->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ field_caps = maep->em_outer_rule_field_caps;
+ desc_setp = __efx_mae_outer_rule_mv_desc_set;
+ desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ mvpl = left->emms_mask_value_pairs.outer;
+ mvpr = right->emms_mask_value_pairs.outer;
+ break;
case EFX_MAE_RULE_ACTION:
field_caps = maep->em_action_rule_field_caps;
desc_setp = __efx_mae_action_rule_mv_desc_set;
return (0);
}
- for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
+ for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
+ ++field_id) {
const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
-
- if (descp->emmd_mask_size == 0)
+ const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
+ const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
+ size_t mask_size = descp->emmd_mask_size;
+ const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
+ const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
+ size_t value_size = descp->emmd_value_size;
+
+ if (mask_size == 0)
continue; /* Skip array gap */
- if (field_cap_id >= field_ncaps)
- break;
+ if ((unsigned int)field_cap_id >= field_ncaps) {
+ /*
+ * The FW has not reported capability status for this
+ * field. It's unknown whether any difference between
+ * the two masks / values affects the class. The only
+ * case when the class must be the same is when these
+ * mask-value pairs match. Otherwise, report mismatch.
+ */
+ if ((memcmp(lmaskp, rmaskp, mask_size) == 0) &&
+ (memcmp(lvalp, rvalp, value_size) == 0))
+ continue;
+ else
+ break;
+ }
if (field_caps[field_cap_id].emfc_mask_affects_class) {
- const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
- const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
- size_t mask_size = descp->emmd_mask_size;
-
if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
have_same_class = B_FALSE;
break;
}
if (field_caps[field_cap_id].emfc_match_affects_class) {
- const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
- const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
- size_t value_size = descp->emmd_value_size;
-
if (memcmp(lvalp, rvalp, value_size) != 0) {
have_same_class = B_FALSE;
break;
return (0);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_outer_rule_insert(
+ __in efx_nic_t *enp,
+ __in const efx_mae_match_spec_t *spec,
+ __in efx_tunnel_protocol_t encap_type,
+ __out efx_mae_rule_id_t *or_idp)
+{
+ const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
+ efx_mcdi_req_t req;
+ EFX_MCDI_DECLARE_BUF(payload,
+ MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
+ MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
+ uint32_t encap_type_mcdi;
+ efx_mae_rule_id_t or_id;
+ size_t offset;
+ efx_rc_t rc;
+
+ EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
+ MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
+
+ EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
+ MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
+
+ if (encp->enc_mae_supported == B_FALSE) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if (spec->emms_type != EFX_MAE_RULE_OUTER) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ switch (encap_type) {
+ case EFX_TUNNEL_PROTOCOL_NONE:
+ encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
+ break;
+ case EFX_TUNNEL_PROTOCOL_VXLAN:
+ encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
+ break;
+ case EFX_TUNNEL_PROTOCOL_GENEVE:
+ encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
+ break;
+ case EFX_TUNNEL_PROTOCOL_NVGRE:
+ encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
+ break;
+ default:
+ rc = ENOTSUP;
+ goto fail3;
+ }
+
+ req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req,
+ MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
+
+ MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
+
+ /*
+ * Mask-value pairs have been stored in the byte order needed for the
+ * MCDI request and are thus safe to be copied directly to the buffer.
+ * The library cares about byte order in efx_mae_match_spec_field_set().
+ */
+ EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
+ MAE_ENC_FIELD_PAIRS_LEN);
+ offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
+ memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
+ MAE_ENC_FIELD_PAIRS_LEN);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail4;
+ }
+
+ if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
+ rc = EMSGSIZE;
+ goto fail5;
+ }
+
+ or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
+ if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
+ rc = ENOENT;
+ goto fail6;
+ }
+
+ or_idp->id = or_id.id;
+
+ return (0);
+
+fail6:
+ EFSYS_PROBE(fail6);
+fail5:
+ EFSYS_PROBE(fail5);
+fail4:
+ EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_outer_rule_remove(
+ __in efx_nic_t *enp,
+ __in const efx_mae_rule_id_t *or_idp)
+{
+ const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
+ efx_mcdi_req_t req;
+ EFX_MCDI_DECLARE_BUF(payload,
+ MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
+ MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
+ efx_rc_t rc;
+
+ if (encp->enc_mae_supported == B_FALSE) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
+
+ MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail2;
+ }
+
+ if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
+ or_idp->id) {
+ /* Firmware failed to remove the outer rule. */
+ rc = EAGAIN;
+ goto fail3;
+ }
+
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_match_spec_outer_rule_id_set(
+ __in efx_mae_match_spec_t *spec,
+ __in const efx_mae_rule_id_t *or_idp)
+{
+ uint32_t full_mask = UINT32_MAX;
+ efx_rc_t rc;
+
+ if (spec->emms_type != EFX_MAE_RULE_ACTION) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ if (or_idp == NULL) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
+ sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
+ sizeof (full_mask), (const uint8_t *)&full_mask);
+ if (rc != 0)
+ goto fail3;
+
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
fail2:
EFSYS_PROBE(fail2);
fail1:
git.droids-corp.org / dpdk.git / blobdiff