/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
* Copyright(c) 2007-2019 Solarflare Communications Inc.
*/
return (ENOTSUP);
}
+#if EFSYS_OPT_PCI
+
+ __checkReturn efx_rc_t
+efx_family_probe_bar(
+ __in uint16_t venid,
+ __in uint16_t devid,
+ __in efsys_pci_config_t *espcp,
+ __in const efx_pci_ops_t *epop,
+ __out efx_family_t *efp,
+ __out efx_bar_region_t *ebrp)
+{
+ efx_rc_t rc;
+ unsigned int membar;
+
+ if (venid == EFX_PCI_VENID_XILINX) {
+ switch (devid) {
+#if EFSYS_OPT_RIVERHEAD
+ case EFX_PCI_DEVID_RIVERHEAD:
+ case EFX_PCI_DEVID_RIVERHEAD_VF:
+ rc = rhead_pci_nic_membar_lookup(espcp, epop, ebrp);
+ if (rc == 0)
+ *efp = EFX_FAMILY_RIVERHEAD;
+
+ return (rc);
+#endif /* EFSYS_OPT_RIVERHEAD */
+ default:
+ break;
+ }
+ }
+
+ rc = efx_family(venid, devid, efp, &membar);
+ if (rc == 0) {
+ ebrp->ebr_type = EFX_BAR_TYPE_MEM;
+ ebrp->ebr_index = membar;
+ ebrp->ebr_offset = 0;
+ ebrp->ebr_length = 0;
+ }
+
+ return (rc);
+}
+
+#endif /* EFSYS_OPT_PCI */
#if EFSYS_OPT_SIENA
#endif /* EFSYS_OPT_MEDFORD2 */
+#if EFSYS_OPT_RIVERHEAD
+
+static const efx_nic_ops_t __efx_nic_riverhead_ops = {
+ rhead_nic_probe, /* eno_probe */
+ rhead_board_cfg, /* eno_board_cfg */
+ rhead_nic_set_drv_limits, /* eno_set_drv_limits */
+ rhead_nic_reset, /* eno_reset */
+ rhead_nic_init, /* eno_init */
+ rhead_nic_get_vi_pool, /* eno_get_vi_pool */
+ rhead_nic_get_bar_region, /* eno_get_bar_region */
+ rhead_nic_hw_unavailable, /* eno_hw_unavailable */
+ rhead_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
+#if EFSYS_OPT_DIAG
+ rhead_nic_register_test, /* eno_register_test */
+#endif /* EFSYS_OPT_DIAG */
+ rhead_nic_fini, /* eno_fini */
+ rhead_nic_unprobe, /* eno_unprobe */
+};
+
+#endif /* EFSYS_OPT_RIVERHEAD */
+
__checkReturn efx_rc_t
efx_nic_create(
__in efx_family_t family,
__in efsys_identifier_t *esip,
__in efsys_bar_t *esbp,
+ __in uint32_t fcw_offset,
__in efsys_lock_t *eslp,
__deref_out efx_nic_t **enpp)
{
break;
#endif /* EFSYS_OPT_MEDFORD2 */
+#if EFSYS_OPT_RIVERHEAD
+ case EFX_FAMILY_RIVERHEAD:
+ enp->en_enop = &__efx_nic_riverhead_ops;
+ enp->en_features =
+ EFX_FEATURE_IPV6 |
+ EFX_FEATURE_LINK_EVENTS |
+ EFX_FEATURE_PERIODIC_MAC_STATS |
+ EFX_FEATURE_MCDI |
+ EFX_FEATURE_MAC_HEADER_FILTERS |
+ EFX_FEATURE_MCDI_DMA;
+ enp->en_arch.ef10.ena_fcw_base = fcw_offset;
+ break;
+#endif /* EFSYS_OPT_RIVERHEAD */
+
default:
rc = ENOTSUP;
goto fail2;
}
+ if ((family != EFX_FAMILY_RIVERHEAD) && (fcw_offset != 0)) {
+ rc = EINVAL;
+ goto fail3;
+ }
+
enp->en_family = family;
enp->en_esip = esip;
enp->en_esbp = esbp;
return (0);
+fail3:
+ EFSYS_PROBE(fail3);
fail2:
EFSYS_PROBE(fail2);
__in efx_nic_t *enp,
__in efx_fw_variant_t efv)
{
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
const efx_nic_ops_t *enop;
efx_rc_t rc;
if ((rc = enop->eno_probe(enp)) != 0)
goto fail1;
+ encp->enc_features = enp->en_features;
+
if ((rc = efx_phy_probe(enp)) != 0)
goto fail2;
return (0);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_nic_get_board_info(
+ __in efx_nic_t *enp,
+ __out efx_nic_board_info_t *board_infop)
+{
+ efx_mcdi_version_t ver;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
+ EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
+
+ rc = efx_mcdi_get_version(enp, EFX_MCDI_VERSION_BOARD_INFO, &ver);
+ if (rc == EMSGSIZE) {
+ /*
+ * Typically, EMSGSIZE is returned by above call in the
+ * case when the NIC does not provide extra information.
+ */
+ rc = ENOTSUP;
+ goto fail1;
+ } else if (rc != 0) {
+ goto fail2;
+ }
+
+ if ((ver.emv_flags & EFX_MCDI_VERSION_BOARD_INFO) == 0) {
+ rc = ENOTSUP;
+ goto fail3;
+ }
+
+ memcpy(board_infop, &ver.emv_board_info, sizeof (*board_infop));
+
+ /* MCDI should provide NUL-terminated strings, but stay vigilant. */
+ board_infop->enbi_serial[sizeof (board_infop->enbi_serial) - 1] = '\0';
+ board_infop->enbi_name[sizeof (board_infop->enbi_name) - 1] = '\0';
+
+ return (0);
+
fail3:
EFSYS_PROBE(fail3);
fail2: