/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
* Copyright(c) 2008-2019 Solarflare Communications Inc.
*/
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
- * rebuild this file with "make -C doc mcdiheaders".
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
+ * rebuild this file with "make mcdi_headers_v5".
*/
#ifndef _SIENA_MC_DRIVER_PCOL_AOE_H
* Perform an FC operation
*/
#define MC_CMD_FC 0x9
+#define MC_CMD_FC_MSGSET 0x9
/* MC_CMD_FC_IN msgrequest */
#define MC_CMD_FC_IN_LEN 4
#define MC_CMD_FC_IN_OP_HDR_OFST 0
#define MC_CMD_FC_IN_OP_HDR_LEN 4
+#define MC_CMD_FC_IN_OP_OFST 0
#define MC_CMD_FC_IN_OP_LBN 0
#define MC_CMD_FC_IN_OP_WIDTH 8
/* enum: NULL MCDI command to FC. */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_MAC_HEADER_OFST 4
#define MC_CMD_FC_IN_MAC_HEADER_LEN 4
+#define MC_CMD_FC_IN_MAC_OP_OFST 4
#define MC_CMD_FC_IN_MAC_OP_LBN 0
#define MC_CMD_FC_IN_MAC_OP_WIDTH 8
/* enum: MAC reconfigure handler */
#define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7
/* enum: MAC Read status */
#define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8
+#define MC_CMD_FC_IN_MAC_PORT_TYPE_OFST 4
#define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8
#define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8
/* enum: External FPGA port. */
#define MC_CMD_FC_PORT_EXT 0x0
/* enum: Internal Siena-facing FPGA ports. */
#define MC_CMD_FC_PORT_INT 0x1
+#define MC_CMD_FC_IN_MAC_PORT_IDX_OFST 4
#define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16
#define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8
+#define MC_CMD_FC_IN_MAC_CMD_FORMAT_OFST 4
#define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24
#define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8
/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LBN 128
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LBN 160
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1
+#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_OFST 24
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1
#define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28
#define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4
#define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12
#define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4
+#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_OFST 12
#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0
#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1
+#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_OFST 12
#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1
#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1
+#define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_OFST 12
#define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2
#define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1
/* Number of statistics to read */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4
#define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4
+#define MC_CMD_FC_IN_DDR_TEST_OP_OFST 4
#define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0
#define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8
/* enum: DRAM Test Start */
/* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */
#define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8
#define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4
+#define MC_CMD_FC_IN_DDR_TEST_START_T0_OFST 8
#define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0
#define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1
+#define MC_CMD_FC_IN_DDR_TEST_START_T1_OFST 8
#define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1
#define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1
+#define MC_CMD_FC_IN_DDR_TEST_START_B0_OFST 8
#define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2
#define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1
+#define MC_CMD_FC_IN_DDR_TEST_START_B1_OFST 8
#define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3
#define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4
#define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4
+#define MC_CMD_FC_IN_READ_MAP_OP_OFST 4
#define MC_CMD_FC_IN_READ_MAP_OP_LBN 0
#define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8
/* enum: Get the number of map regions */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4
+#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0
#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1
+#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1
#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1
+#define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2
#define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1
+#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3
#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1
+#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1
+#define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_OFST 4
#define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5
#define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4
#define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4
+#define MC_CMD_FC_IN_IO_REL_OP_OFST 4
#define MC_CMD_FC_IN_IO_REL_OP_LBN 0
#define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8
/* enum: Get the base address that the FC applies to relative commands */
#define MC_CMD_FC_IN_IO_REL_READ32 0x2
/* enum: Write data */
#define MC_CMD_FC_IN_IO_REL_WRITE32 0x3
+#define MC_CMD_FC_IN_IO_REL_COMP_TYPE_OFST 4
#define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8
#define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8
/* enum: Application address space */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4
#define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4
+#define MC_CMD_FC_IN_UHLINK_OP_OFST 4
#define MC_CMD_FC_IN_UHLINK_OP_LBN 0
#define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8
/* enum: Get PHY configuration info */
#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7
/* enum: Get loopback mode config state on fpga port */
#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8
+#define MC_CMD_FC_IN_UHLINK_PORT_TYPE_OFST 4
#define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8
#define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8
+#define MC_CMD_FC_IN_UHLINK_PORT_IDX_OFST 4
#define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16
#define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8
+#define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_OFST 4
#define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24
#define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8
/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
#define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4
#define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12
#define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4
+#define MC_CMD_FC_IN_SET_LINK_LOWPOWER_OFST 12
#define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0
#define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1
+#define MC_CMD_FC_IN_SET_LINK_POWEROFF_OFST 12
#define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1
#define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1
+#define MC_CMD_FC_IN_SET_LINK_TXDIS_OFST 12
#define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2
#define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LBN 160
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LBN 192
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4
#define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4
#define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44
#define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_OFST 44
#define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0
#define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1
+#define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_OFST 44
#define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1
#define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1
+#define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_OFST 44
#define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2
#define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1
+#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_OFST 44
#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3
#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2
#define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LBN 96
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LBN 128
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LBN 96
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LBN 128
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_WIDTH 32
/* Port number of PTP packet for which timestamp required */
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
#define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
/* MC_CMD_FC_OUT_MAC msgresponse */
#define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8
#define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_OFST 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8
/* enum: Test not yet initiated */
#define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2
/* enum: Test did not complete in specified time */
#define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_OFST 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_OFST 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_OFST 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_OFST 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8
#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1
/* Test result from FPGA */
#define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28
#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15
#define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10
#define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5
#define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5
+#define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_OFST 4
#define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0
#define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5
#define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */
/* Assertion status flag. */
#define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0
#define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4
+#define MC_CMD_FC_OUT_GET_ASSERT_STATE_OFST 0
#define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8
#define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8
/* enum: No crash data available */
#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1
/* enum: Crash data has been sent */
#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2
+#define MC_CMD_FC_OUT_GET_ASSERT_TYPE_OFST 0
#define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0
#define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8
/* enum: No crash has been recorded. */
#define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32
#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31
#define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30
#define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14
+#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8
+#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4
/* Build timestamp (seconds since epoch) */
#define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8
#define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */
#define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10
+#define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18
#define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27
#define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28
#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2
+#define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31
#define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1
#define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */
#define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20
#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_OFST 20
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_OFST 20
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LBN 128
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LBN 160
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_OFST 28
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_OFST 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4
/* Build timestamp (seconds since epoch) */
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_OFST 8
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4
#define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */
#define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_OFST 12
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1
/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_OFST 20
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_OFST 20
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_OFST 28
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0
#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32
#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31
#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30
#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14
+#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4
#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8
+#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4
/* Build timestamp (seconds since epoch) */
#define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4
#define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27
#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28
#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29
#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30
#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31
#define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_OFST 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_OFST 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_OFST 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_OFST 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20
#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_OFST 20
#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_OFST 20
#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24
#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28
#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_OFST 28
#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_OFST 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4
/* Build timestamp (seconds since epoch) */
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_OFST 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_OFST 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_OFST 12
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1
/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_OFST 28
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0
#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16
/* Qsys system ID */
#define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0
#define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4
+#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_OFST 0
#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12
#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4
+#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_OFST 0
#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4
#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8
+#define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_OFST 0
#define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0
#define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LBN 64
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LBN 96
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_WIDTH 32
/* Length of address map */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LBN 128
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LBN 160
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_WIDTH 32
/* Component information field */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LBN 224
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LBN 256
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_WIDTH 32
/* Name of the component */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
#define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_OFST 0
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16
+#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_OFST 0
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16
/* Transceiver Transmit settings */
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_OFST 4
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16
+#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_OFST 4
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16
/* Transceiver Receive settings */
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_OFST 8
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16
+#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_OFST 8
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16
#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16
/* Rx eye opening */
#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12
#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_OFST 12
#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0
#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16
+#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_OFST 12
#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16
#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16
/* PCS status word */
/* Link status word */
#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20
#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_OFST 20
#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0
#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1
+#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_OFST 20
#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1
#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1
/* Current SFp parameters applied */
/* PHY config flags */
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_OFST 44
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1
+#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_OFST 44
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1
+#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_OFST 44
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2
#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LBN 96
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LBN 128
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_WIDTH 32
/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
#define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LBN 32
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LBN 64
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
/* Capabilities of the FPGA/FC */
#define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0
#define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4
+#define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_OFST 0
#define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0
#define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LBN 32
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LBN 64
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LBN 288
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LBN 320
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_WIDTH 32
/* When active, end read time */
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LBN 352
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LBN 384
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_WIDTH 32
/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
#define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LBN 32
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LBN 64
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
#define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4
#define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0
#define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4
+#define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_OFST 0
#define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0
#define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1
+#define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_OFST 0
#define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1
#define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LBN 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LBN 32
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127
/* DDR soak test status word; bits [4:0] are relevant. */
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4
+#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_OFST 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1
+#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_OFST 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1
+#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_OFST 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1
+#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_OFST 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1
+#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_OFST 0
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4
#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1
/* DDR soak test error count */
* AOE operations on MC
*/
#define MC_CMD_AOE 0xa
+#define MC_CMD_AOE_MSGSET 0xa
/* MC_CMD_AOE_IN msgrequest */
#define MC_CMD_AOE_IN_LEN 4
#define MC_CMD_AOE_IN_OP_HDR_OFST 0
#define MC_CMD_AOE_IN_OP_HDR_LEN 4
+#define MC_CMD_AOE_IN_OP_OFST 0
#define MC_CMD_AOE_IN_OP_LBN 0
#define MC_CMD_AOE_IN_OP_WIDTH 8
/* enum: FPGA and CPLD information */
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LBN 64
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LBN 96
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0
#define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1
+#define MC_CMD_AOE_IN_MAC_STATS_CLEAR_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1
#define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1
+#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1
+#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1
+#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1
+#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5
#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1
+#define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16
#define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16
/* Length of DMA data (optional) */
/* MC_CMD_AOE_IN_CMD_LEN 4 */
#define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4
#define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4
+#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_OFST 4
#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
/* enum: AOE and associated external port */
#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2
/* enum: Configure link state mode on given AOE port */
#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3
+#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_OFST 4
#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
/* enum: No-op */
#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1
/* enum: logical AND of all SFP ports link status */
#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2
+#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_OFST 4
#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16
/* FC boot control flags */
#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4
#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4
+#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_OFST 4
#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0
#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1
/* Assertion status flag. */
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4
+#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_OFST 0
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8
/* enum: No crash data available */
/* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */
/* enum: Crash data has been sent */
/* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */
+#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_OFST 0
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8
/* enum: No crash has been recorded. */
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
/* Information on the module. */
#define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
#define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4
+#define MC_CMD_AOE_OUT_DDR_PRESENT_OFST 0
#define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0
#define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1
+#define MC_CMD_AOE_OUT_DDR_POWERED_OFST 0
#define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1
#define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1
+#define MC_CMD_AOE_OUT_DDR_OPERATIONAL_OFST 0
#define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2
#define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1
+#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_OFST 0
#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3
#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1
/* Memory size, in MB. */
/* Flags describing status info on the module. */
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_OFST 0
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1
/* DDR ECC status on the module. */
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8
+#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_OFST 4
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24
#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8
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