common/sfc_efx/base: add missing MCDI response length checks

[dpdk.git] / drivers / common / sfc_efx / base / efx_tx.c

diff --git a/drivers/common/sfc_efx/base/efx_tx.c b/drivers/common/sfc_efx/base/efx_tx.c
index 38c64e0..6f61f93 100644 (file)
--- a/drivers/common/sfc_efx/base/efx_tx.c
+++ b/drivers/common/sfc_efx/base/efx_tx.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
  * Copyright(c) 2007-2019 Solarflare Communications Inc.
  */
 
@@ -205,6 +205,33 @@ static const efx_tx_ops_t  __efx_tx_medford2_ops = {
 };
 #endif /* EFSYS_OPT_MEDFORD2 */
 
+#if EFSYS_OPT_RIVERHEAD
+static const efx_tx_ops_t      __efx_tx_rhead_ops = {
+       rhead_tx_init,                          /* etxo_init */
+       rhead_tx_fini,                          /* etxo_fini */
+       rhead_tx_qcreate,                       /* etxo_qcreate */
+       rhead_tx_qdestroy,                      /* etxo_qdestroy */
+       rhead_tx_qpost,                         /* etxo_qpost */
+       rhead_tx_qpush,                         /* etxo_qpush */
+       rhead_tx_qpace,                         /* etxo_qpace */
+       rhead_tx_qflush,                        /* etxo_qflush */
+       rhead_tx_qenable,                       /* etxo_qenable */
+       NULL,                                   /* etxo_qpio_enable */
+       NULL,                                   /* etxo_qpio_disable */
+       NULL,                                   /* etxo_qpio_write */
+       NULL,                                   /* etxo_qpio_post */
+       rhead_tx_qdesc_post,                    /* etxo_qdesc_post */
+       NULL,                                   /* etxo_qdesc_dma_create */
+       NULL,                                   /* etxo_qdesc_tso_create */
+       NULL,                                   /* etxo_qdesc_tso2_create */
+       NULL,                                   /* etxo_qdesc_vlantci_create */
+       NULL,                                   /* etxo_qdesc_checksum_create */
+#if EFSYS_OPT_QSTATS
+       rhead_tx_qstats_update,                 /* etxo_qstats_update */
+#endif
+};
+#endif /* EFSYS_OPT_RIVERHEAD */
+
 
        __checkReturn   efx_rc_t
 efx_tx_init(
@@ -251,6 +278,12 @@ efx_tx_init(
                break;
 #endif /* EFSYS_OPT_MEDFORD2 */
 
+#if EFSYS_OPT_RIVERHEAD
+       case EFX_FAMILY_RIVERHEAD:
+               etxop = &__efx_tx_rhead_ops;
+               break;
+#endif /* EFSYS_OPT_RIVERHEAD */
+
        default:
                EFSYS_ASSERT(0);
                rc = ENOTSUP;
@@ -833,7 +866,7 @@ siena_tx_qpush(
 
        /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
        EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
-           wptr, pushed & etp->et_mask);
+           SIENA_TXQ_DESC_SIZE, wptr, pushed & etp->et_mask);
        EFSYS_PIO_WRITE_BARRIER();
        EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,
                            etp->et_index, &dword, B_FALSE);