common/sfc_efx/base: fix PHY config failure on Riverhead

[dpdk.git] / drivers / common / sfc_efx / base / rhead_nic.c

diff --git a/drivers/common/sfc_efx/base/rhead_nic.c b/drivers/common/sfc_efx/base/rhead_nic.c
index 7fb28ea..66db68b 100644 (file)
--- a/drivers/common/sfc_efx/base/rhead_nic.c
+++ b/drivers/common/sfc_efx/base/rhead_nic.c
@@ -22,6 +22,23 @@ rhead_board_cfg(
        if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)
                goto fail1;
 
+       /*
+        * The tunnel encapsulation initialization happens unconditionally
+        * for now.
+        */
+       encp->enc_tunnel_encapsulations_supported =
+           (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
+           (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
+           (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
+
+       /*
+        * Software limitation inherited from EF10. This limit is not
+        * increased since the hardware does not report this limit, it is
+        * handled internally resulting in a tunnel add error when there is no
+        * space for more UDP tunnels.
+        */
+       encp->enc_tunnel_config_udp_entries_max = EFX_TUNNEL_MAXNENTRIES;
+
        encp->enc_clk_mult = 1; /* not used for Riverhead */
 
        /*
@@ -112,6 +129,12 @@ rhead_board_cfg(
        encp->enc_evq_timer_quantum_ns = 0;
        encp->enc_evq_timer_max_us = 0;
 
+#if EFSYS_OPT_EV_EXTENDED_WIDTH
+       encp->enc_ev_ew_desc_size = RHEAD_EVQ_EW_DESC_SIZE;
+#else
+       encp->enc_ev_ew_desc_size = 0;
+#endif
+
        encp->enc_ev_desc_size = RHEAD_EVQ_DESC_SIZE;
        encp->enc_rx_desc_size = RHEAD_RXQ_DESC_SIZE;
        encp->enc_tx_desc_size = RHEAD_TXQ_DESC_SIZE;
@@ -319,6 +342,7 @@ rhead_nic_init(
        uint32_t vi_count, vi_base, vi_shift;
        uint32_t vi_window_size;
        efx_rc_t rc;
+       boolean_t alloc_vadaptor = B_TRUE;
 
        EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
        EFSYS_ASSERT3U(edcp->edc_max_piobuf_count, ==, 0);
@@ -370,12 +394,34 @@ rhead_nic_init(
        enp->en_arch.ef10.ena_wc_mem_map_offset = 0;
        enp->en_arch.ef10.ena_wc_mem_map_size = 0;
 
-       enp->en_vport_id = EVB_PORT_ID_NULL;
-
        enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
 
+       /*
+        * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
+        * during NIC initialization when vSwitch is created and vPorts are
+        * allocated. Hence, skip vAdaptor allocation for EVB and update vPort
+        * ID in NIC structure with the one allocated for PF.
+        */
+
+       enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
+#if EFSYS_OPT_EVB
+       if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
+               /* For EVB use vPort allocated on vSwitch */
+               enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
+               alloc_vadaptor = B_FALSE;
+       }
+#endif
+       if (alloc_vadaptor != B_FALSE) {
+               /* Allocate a vAdaptor attached to our upstream vPort/pPort */
+               if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
+                       goto fail5;
+       }
+
        return (0);
 
+fail5:
+       EFSYS_PROBE(fail5);
+
 fail4:
        EFSYS_PROBE(fail4);
 
@@ -456,7 +502,7 @@ rhead_nic_hw_unavailable(
        if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
                return (B_TRUE);
 
-       EFX_BAR_READD(enp, ER_GZ_MC_SFT_STATUS, &dword, B_FALSE);
+       EFX_BAR_FCW_READD(enp, ER_GZ_MC_SFT_STATUS, &dword);
        if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
                goto unavail;
 
@@ -480,6 +526,22 @@ rhead_nic_set_hw_unavailable(
 rhead_nic_fini(
        __in            efx_nic_t *enp)
 {
+       boolean_t do_vadaptor_free = B_TRUE;
+
+#if EFSYS_OPT_EVB
+       if (enp->en_vswitchp != NULL) {
+               /*
+                * For SR-IOV the vAdaptor is freed with the vSwitch,
+                * so do not free it here.
+                */
+               do_vadaptor_free = B_FALSE;
+       }
+#endif
+       if (do_vadaptor_free != B_FALSE) {
+               (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
+               enp->en_vport_id = EVB_PORT_ID_NULL;
+       }
+
        (void) efx_mcdi_free_vis(enp);
        enp->en_arch.ef10.ena_vi_count = 0;
 }
@@ -518,4 +580,54 @@ fail1:
 
 #endif /* EFSYS_OPT_DIAG */
 
+       __checkReturn                   efx_rc_t
+rhead_nic_xilinx_cap_tbl_read_ef100_locator(
+       __in                            efsys_bar_t *esbp,
+       __in                            efsys_dma_addr_t offset,
+       __out                           efx_bar_region_t *ebrp)
+{
+       efx_oword_t entry;
+       uint32_t rev;
+       uint32_t len;
+       efx_rc_t rc;
+
+       /*
+        * Xilinx Capabilities Table requires 32bit aligned reads.
+        * See SF-119689-TC section 4.2.2 "Discovery Steps".
+        */
+       EFSYS_BAR_READD(esbp, offset +
+                       (EFX_LOW_BIT(ESF_GZ_CFGBAR_ENTRY_FORMAT) / 8),
+                       &entry.eo_dword[0], B_FALSE);
+       EFSYS_BAR_READD(esbp, offset +
+                       (EFX_LOW_BIT(ESF_GZ_CFGBAR_ENTRY_SIZE) / 8),
+                       &entry.eo_dword[1], B_FALSE);
+
+       rev = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_ENTRY_REV);
+       len = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_ENTRY_SIZE);
+
+       if (rev != ESE_GZ_CFGBAR_ENTRY_REV_EF100 ||
+           len < ESE_GZ_CFGBAR_ENTRY_SIZE_EF100) {
+               rc = EINVAL;
+               goto fail1;
+       }
+
+       EFSYS_BAR_READD(esbp, offset +
+                       (EFX_LOW_BIT(ESF_GZ_CFGBAR_EF100_BAR) / 8),
+                       &entry.eo_dword[2], B_FALSE);
+
+       ebrp->ebr_index = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_EF100_BAR);
+       ebrp->ebr_offset = EFX_OWORD_FIELD32(entry,
+                       ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF) <<
+                       ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT;
+       ebrp->ebr_type = EFX_BAR_TYPE_MEM;
+       ebrp->ebr_length = 0;
+
+       return (0);
+
+fail1:
+       EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+       return (rc);
+}
+
 #endif /* EFSYS_OPT_RIVERHEAD */