/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
* Copyright(c) 2009-2019 Solarflare Communications Inc.
*/
encp->enc_rx_scale_additional_modes_supported = B_FALSE;
#endif /* EFSYS_OPT_RX_SCALE */
+ /*
+ * Event queue creation is complete when an
+ * EVQ_INIT_DONE_EV event is received.
+ */
+ encp->enc_evq_init_done_ev_supported = B_TRUE;
+
encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
/* Fragments must not span 4k boundaries. */
encp->enc_tx_dma_desc_boundary = 4096;
encp->enc_fw_assisted_tso_enabled = B_FALSE;
encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
encp->enc_fw_assisted_tso_v2_n_contexts = 0;
+ encp->enc_tso_v3_enabled = B_FALSE;
+ encp->enc_rx_scatter_max = -1;
encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
encp->enc_rx_packed_stream_supported = B_FALSE;
encp->enc_rx_var_packed_stream_supported = B_FALSE;
encp->enc_filter_action_mark_supported = B_FALSE;
encp->enc_filter_action_mark_max = 0;
+ encp->enc_mae_supported = B_FALSE;
+
return (0);
fail2:
__in efx_nic_t *enp)
{
efx_port_t *epp = &(enp->en_port);
- efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
siena_link_state_t sls;
unsigned int mask;
efx_oword_t oword;
goto fail12;
#endif
- encp->enc_features = enp->en_features;
-
return (0);
#if EFSYS_OPT_MON_STATS