common/cnxk: support matching VLAN existence

[dpdk.git] / drivers / common / sfc_efx / efsys.h

diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h
index 139f4d8..224254b 100644 (file)
--- a/drivers/common/sfc_efx/efsys.h
+++ b/drivers/common/sfc_efx/efsys.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
  * Copyright(c) 2016-2019 Solarflare Communications Inc.
  *
  * This software was jointly developed between OKTET Labs (under contract
@@ -39,8 +39,25 @@ extern "C" {
 
 #define EFSYS_HAS_UINT64 1
 #define EFSYS_USE_UINT64 1
+/*
+ * __SSE2__ is defined by a compiler if target architecture supports
+ * Streaming SIMD Extensions 2 (SSE2). __m128i is a data type used
+ * by the extension instructions.
+ */
+#if defined(__SSE2__)
 #define EFSYS_HAS_UINT128 1
 typedef __m128i efsys_uint128_t;
+/*
+ * __int128 and unsigned __int128 are compiler extensions (built-in types).
+ * __SIZEOF_INT128__ is defined by the compiler if these data types are
+ * available.
+ */
+#elif defined(__SIZEOF_INT128__)
+#define EFSYS_HAS_UINT128 1
+typedef unsigned __int128 efsys_uint128_t;
+#else
+#error Unsigned 128-bit width integers support is required
+#endif
 
 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 #define EFSYS_IS_BIG_ENDIAN 1
@@ -108,7 +125,7 @@ prefetch_read_once(const volatile void *addr)
 /* Enable Riverhead support */
 #define EFSYS_OPT_RIVERHEAD 1
 
-#ifdef RTE_LIBRTE_SFC_EFX_DEBUG
+#ifdef RTE_DEBUG_COMMON_SFC_EFX
 #define EFSYS_OPT_CHECK_REG 1
 #else
 #define EFSYS_OPT_CHECK_REG 0
@@ -170,6 +187,8 @@ prefetch_read_once(const volatile void *addr)
 
 #define EFSYS_OPT_MAE 1
 
+#define EFSYS_OPT_VIRTIO 1
+
 /* ID */
 
 typedef struct __efsys_identifier_s efsys_identifier_t;
@@ -590,14 +609,14 @@ typedef struct efsys_bar_s {
 /* DMA SYNC */
 
 /*
- * DPDK does not provide any DMA syncing API, and no PMD drivers
+ * DPDK does not provide any DMA syncing API, and no PMDs
  * have any traces of explicit DMA syncing.
  * DMA mapping is assumed to be coherent.
  */
 
 #define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size)       ((void)0)
 
-/* Just avoid store and compiler (impliciltly) reordering */
+/* Just avoid store and compiler (implicitly) reordering */
 #define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size)       rte_wmb()
 
 /* TIMESTAMP */
@@ -723,7 +742,7 @@ typedef uint64_t    efsys_stat_t;
 /* RTE_VERIFY from DPDK treats expressions with % operator incorrectly,
  * so we re-implement it here
  */
-#ifdef RTE_LIBRTE_SFC_EFX_DEBUG
+#ifdef RTE_DEBUG_COMMON_SFC_EFX
 #define EFSYS_ASSERT(_exp)                                             \
        do {                                                            \
                if (unlikely(!(_exp)))                                  \