static const struct rte_compressdev_capabilities isal_pmd_capabilities[] = {
{
.algo = RTE_COMP_ALGO_DEFLATE,
- .comp_feature_flags = RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+ .comp_feature_flags = RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
+ RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
+ RTE_COMP_FF_OOP_LB_IN_SGL_OUT |
+ RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
- RTE_COMP_FF_HUFFMAN_DYNAMIC,
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
+ RTE_COMP_FF_CRC32_CHECKSUM |
+ RTE_COMP_FF_ADLER32_CHECKSUM,
.window_size = {
.min = 15,
.max = 15,
{
if (dev_info != NULL) {
dev_info->capabilities = isal_pmd_capabilities;
- dev_info->feature_flags = RTE_COMPDEV_FF_CPU_AVX512 |
- RTE_COMPDEV_FF_CPU_AVX2 |
- RTE_COMPDEV_FF_CPU_AVX |
- RTE_COMPDEV_FF_CPU_SSE;
+
+ /* Check CPU for supported vector instruction and set
+ * feature_flags
+ */
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
+ dev_info->feature_flags |= RTE_COMPDEV_FF_CPU_AVX512;
+ else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
+ dev_info->feature_flags |= RTE_COMPDEV_FF_CPU_AVX2;
+ else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
+ dev_info->feature_flags |= RTE_COMPDEV_FF_CPU_AVX;
+ else
+ dev_info->feature_flags |= RTE_COMPDEV_FF_CPU_SSE;
}
}
if (qp == NULL)
return -EINVAL;
- if (qp->stream != NULL)
- rte_free(qp->stream);
-
- if (qp->stream->level_buf != NULL)
+ if (qp->stream)
rte_free(qp->stream->level_buf);
- if (qp->state != NULL)
- rte_free(qp->state);
-
- if (dev->data->queue_pairs[qp_id] != NULL)
- rte_free(dev->data->queue_pairs[qp_id]);
+ rte_free(qp->state);
+ rte_ring_free(qp->processed_pkts);
+ rte_free(qp->stream);
+ rte_free(qp);
+ dev->data->queue_pairs[qp_id] = NULL;
return 0;
}
struct isal_comp_qp *qp)
{
unsigned int n = snprintf(qp->name, sizeof(qp->name),
- "isal_compression_pmd_%u_qp_%u",
+ "isal_comp_pmd_%u_qp_%u",
dev->data->dev_id, qp->id);
if (n >= sizeof(qp->name))