net/ice: clean input set macro definition

[dpdk.git] / drivers / compress / mlx5 / mlx5_compress.c

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 25f7182..46255ab 100644 (file)
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -76,8 +76,28 @@ static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
 
 int mlx5_compress_logtype;
 
-const struct rte_compressdev_capabilities mlx5_caps[RTE_COMP_ALGO_LIST_END];
-
+static const struct rte_compressdev_capabilities mlx5_caps[] = {
+       {
+               .algo = RTE_COMP_ALGO_NULL,
+               .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
+                                     RTE_COMP_FF_CRC32_CHECKSUM |
+                                     RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+                                     RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
+       },
+       {
+               .algo = RTE_COMP_ALGO_DEFLATE,
+               .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
+                                     RTE_COMP_FF_CRC32_CHECKSUM |
+                                     RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+                                     RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+                                     RTE_COMP_FF_HUFFMAN_FIXED |
+                                     RTE_COMP_FF_HUFFMAN_DYNAMIC,
+               .window_size = {.min = 10, .max = 15, .increment = 1},
+       },
+       {
+               .algo = RTE_COMP_ALGO_LIST_END,
+       }
+};
 
 static void
 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
@@ -594,7 +614,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
                        op->consumed = op->src.length;
                        op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
                        MLX5_ASSERT(cqe->byte_cnt ==
-                                   qp->opaque_buf[idx].scattered_length);
+                                   opaq[idx].scattered_length);
                        switch (xform->csum_type) {
                        case RTE_COMP_CHECKSUM_CRC32:
                                op->output_chksum = (uint64_t)rte_be_to_cpu_32
@@ -711,7 +731,7 @@ mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
                return -1;
        }
        priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
-       MLX5_ASSERT(qp->uar_addr);
+       MLX5_ASSERT(priv->uar_addr);
 #ifndef RTE_ARCH_64
        rte_spinlock_init(&priv->uar32_sl);
 #endif /* RTE_ARCH_64 */