/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2016-2017 Intel Corporation
+ * Copyright(c) 2016-2020 Intel Corporation
*/
-#ifndef _RTE_AESNI_GCM_PMD_PRIVATE_H_
-#define _RTE_AESNI_GCM_PMD_PRIVATE_H_
+#ifndef _AESNI_GCM_PMD_PRIVATE_H_
+#define _AESNI_GCM_PMD_PRIVATE_H_
#include "aesni_gcm_ops.h"
+/*
+ * IMB_VERSION_NUM macro was introduced in version Multi-buffer 0.50,
+ * so if macro is not defined, it means that the version is 0.49.
+ */
+#if !defined(IMB_VERSION_NUM)
+#define IMB_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c))
+#define IMB_VERSION_NUM IMB_VERSION(0, 49, 0)
+#endif
+
#define CRYPTODEV_NAME_AESNI_GCM_PMD crypto_aesni_gcm
/**< AES-NI GCM PMD device name */
/** AES-NI GCM PMD LOGTYPE DRIVER */
-int aesni_gcm_logtype_driver;
+extern int aesni_gcm_logtype_driver;
#define AESNI_GCM_LOG(level, fmt, ...) \
rte_log(RTE_LOG_ ## level, aesni_gcm_logtype_driver, \
"%s() line %u: "fmt "\n", __func__, __LINE__, \
/**< Vector mode */
unsigned max_nb_queue_pairs;
/**< Max number of queue pairs supported by device */
+ MB_MGR *mb_mgr;
+ /**< Multi-buffer instance */
+ struct aesni_gcm_ops ops[GCM_KEY_NUM];
+ /**< Function pointer table of the gcm APIs */
};
struct aesni_gcm_qp {
const struct aesni_gcm_ops *ops;
- /**< Architecture dependent function pointer table of the gcm APIs */
+ /**< Function pointer table of the gcm APIs */
struct rte_ring *processed_pkts;
/**< Ring for placing process packets */
struct gcm_context_data gdata_ctx; /* (16 * 5) + 8 = 88 B */
/**< Queue pair statistics */
struct rte_mempool *sess_mp;
/**< Session Mempool */
+ struct rte_mempool *sess_mp_priv;
+ /**< Session Private Data Mempool */
uint16_t id;
/**< Queue Pair Identifier */
char name[RTE_CRYPTODEV_NAME_MAX_LEN];
/**< IV parameters */
uint16_t aad_length;
/**< AAD length */
- uint16_t digest_length;
- /**< Digest length */
+ uint16_t req_digest_length;
+ /**< Requested digest length */
+ uint16_t gen_digest_length;
+ /**< Generated digest length */
enum aesni_gcm_operation op;
/**< GCM operation type */
enum aesni_gcm_key key;
/**< GCM key type */
struct gcm_key_data gdata_key;
/**< GCM parameters */
+ struct aesni_gcm_session_ops ops;
+ /**< Session handlers */
};
struct aesni_gcm_session *sess,
const struct rte_crypto_sym_xform *xform);
-
-/**
- * Device specific operations function pointer structure */
+/* Device specific operations function pointer structure */
extern struct rte_cryptodev_ops *rte_aesni_gcm_pmd_ops;
+/** CPU crypto bulk process handler */
+uint32_t
+aesni_gcm_pmd_cpu_crypto_process(struct rte_cryptodev *dev,
+ struct rte_cryptodev_sym_session *sess, union rte_crypto_sym_ofs ofs,
+ struct rte_crypto_sym_vec *vec);
-#endif /* _RTE_AESNI_GCM_PMD_PRIVATE_H_ */
+#endif /* _AESNI_GCM_PMD_PRIVATE_H_ */