/*-
* BSD LICENSE
*
- * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
static const struct rte_cryptodev_capabilities aesni_mb_pmd_capabilities[] = {
{ /* MD5 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
.block_size = 64,
.key_size = {
.max = 12,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* SHA1 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
.block_size = 64,
.key_size = {
.max = 12,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* SHA224 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
.block_size = 64,
.key_size = {
.max = 14,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* SHA256 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
.block_size = 64,
.key_size = {
.max = 16,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* SHA384 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
.block_size = 128,
.key_size = {
.max = 24,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* SHA512 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
.block_size = 128,
.key_size = {
.max = 32,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* AES XCBC HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- .auth = {
+ {.auth = {
.algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
.block_size = 16,
.key_size = {
.max = 12,
.increment = 0
},
- .aad_size = { 0 }
- }
- }
+ .aad_size = { 0 },
+ .iv_size = { 0 }
+ }, }
+ }, }
},
{ /* AES CBC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- .sym = {
+ {.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
- .cipher = {
+ {.cipher = {
.algo = RTE_CRYPTO_CIPHER_AES_CBC,
.block_size = 16,
.key_size = {
.max = 16,
.increment = 0
}
- }
- }
+ }, }
+ }, }
+ },
+ { /* AES CTR */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
},
+ { /* AES DOCSIS BPI */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_DOCSISBPI,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
/** Configure device */
static int
-aesni_mb_pmd_config(__rte_unused struct rte_cryptodev *dev)
+aesni_mb_pmd_config(__rte_unused struct rte_cryptodev *dev,
+ __rte_unused struct rte_cryptodev_config *config)
{
return 0;
}
static int
aesni_mb_pmd_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)
{
- if (dev->data->queue_pairs[qp_id] != NULL) {
- rte_free(dev->data->queue_pairs[qp_id]);
+ struct aesni_mb_qp *qp = dev->data->queue_pairs[qp_id];
+ struct rte_ring *r = NULL;
+
+ if (qp != NULL) {
+ r = rte_ring_lookup(qp->name);
+ if (r)
+ rte_ring_free(r);
+ rte_free(qp);
dev->data->queue_pairs[qp_id] = NULL;
}
return 0;
/** Create a ring to place processed operations on */
static struct rte_ring *
aesni_mb_pmd_qp_create_processed_ops_ring(struct aesni_mb_qp *qp,
- unsigned ring_size, int socket_id)
+ const char *str, unsigned int ring_size, int socket_id)
{
struct rte_ring *r;
+ char ring_name[RTE_CRYPTODEV_NAME_LEN];
- r = rte_ring_lookup(qp->name);
+ unsigned int n = snprintf(ring_name, sizeof(ring_name),
+ "%s_%s",
+ qp->name, str);
+
+ if (n > sizeof(ring_name))
+ return NULL;
+
+ r = rte_ring_lookup(ring_name);
if (r) {
- if (r->prod.size >= ring_size) {
+ if (rte_ring_get_size(r) >= ring_size) {
MB_LOG_INFO("Reusing existing ring %s for processed ops",
- qp->name);
+ ring_name);
return r;
}
MB_LOG_ERR("Unable to reuse existing ring %s for processed ops",
- qp->name);
+ ring_name);
return NULL;
}
- return rte_ring_create(qp->name, ring_size, socket_id,
+ return rte_ring_create(ring_name, ring_size, socket_id,
RING_F_SP_ENQ | RING_F_SC_DEQ);
}
if (aesni_mb_pmd_qp_set_unique_name(dev, qp))
goto qp_setup_cleanup;
- qp->ops = &job_ops[internals->vector_mode];
- qp->processed_ops = aesni_mb_pmd_qp_create_processed_ops_ring(qp,
- qp_conf->nb_descriptors, socket_id);
- if (qp->processed_ops == NULL)
+ qp->op_fns = &job_ops[internals->vector_mode];
+
+ qp->ingress_queue = aesni_mb_pmd_qp_create_processed_ops_ring(qp,
+ "ingress", qp_conf->nb_descriptors, socket_id);
+ if (qp->ingress_queue == NULL)
goto qp_setup_cleanup;
qp->sess_mp = dev->data->session_pool;
memset(&qp->stats, 0, sizeof(qp->stats));
/* Initialise multi-buffer manager */
- (*qp->ops->job.init_mgr)(&qp->mb_mgr);
-
+ (*qp->op_fns->job.init_mgr)(&qp->mb_mgr);
return 0;
qp_setup_cleanup:
git.droids-corp.org / dpdk.git / blobdiff