crypto/ccp: support hwrng

[dpdk.git] / drivers / crypto / ccp / ccp_dev.h

diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h
index c360fe0..de375ee 100644 (file)
--- a/drivers/crypto/ccp/ccp_dev.h
+++ b/drivers/crypto/ccp/ccp_dev.h
@@ -21,6 +21,7 @@
 
 /**< CCP sspecific */
 #define MAX_HW_QUEUES                   5
+#define CCP_MAX_TRNG_RETRIES           10
 
 /**< CCP Register Mappings */
 #define Q_MASK_REG                      0x000
@@ -197,8 +198,127 @@ struct ccp_device {
        /**< protection for shared lsb region allocation */
        int qidx;
        /**< current queue index */
+       int hwrng_retries;
+       /**< retry counter for CCP TRNG */
 } __rte_cache_aligned;
 
+/**< CCP H/W engine related */
+/**
+ * ccp_engine - CCP operation identifiers
+ *
+ * @CCP_ENGINE_AES: AES operation
+ * @CCP_ENGINE_XTS_AES: 128-bit XTS AES operation
+ * @CCP_ENGINE_3DES: DES/3DES operation
+ * @CCP_ENGINE_SHA: SHA operation
+ * @CCP_ENGINE_RSA: RSA operation
+ * @CCP_ENGINE_PASSTHRU: pass-through operation
+ * @CCP_ENGINE_ZLIB_DECOMPRESS: unused
+ * @CCP_ENGINE_ECC: ECC operation
+ */
+enum ccp_engine {
+       CCP_ENGINE_AES = 0,
+       CCP_ENGINE_XTS_AES_128,
+       CCP_ENGINE_3DES,
+       CCP_ENGINE_SHA,
+       CCP_ENGINE_RSA,
+       CCP_ENGINE_PASSTHRU,
+       CCP_ENGINE_ZLIB_DECOMPRESS,
+       CCP_ENGINE_ECC,
+       CCP_ENGINE__LAST,
+};
+
+/* Passthru engine */
+/**
+ * ccp_passthru_bitwise - type of bitwise passthru operation
+ *
+ * @CCP_PASSTHRU_BITWISE_NOOP: no bitwise operation performed
+ * @CCP_PASSTHRU_BITWISE_AND: perform bitwise AND of src with mask
+ * @CCP_PASSTHRU_BITWISE_OR: perform bitwise OR of src with mask
+ * @CCP_PASSTHRU_BITWISE_XOR: perform bitwise XOR of src with mask
+ * @CCP_PASSTHRU_BITWISE_MASK: overwrite with mask
+ */
+enum ccp_passthru_bitwise {
+       CCP_PASSTHRU_BITWISE_NOOP = 0,
+       CCP_PASSTHRU_BITWISE_AND,
+       CCP_PASSTHRU_BITWISE_OR,
+       CCP_PASSTHRU_BITWISE_XOR,
+       CCP_PASSTHRU_BITWISE_MASK,
+       CCP_PASSTHRU_BITWISE__LAST,
+};
+
+/**
+ * ccp_passthru_byteswap - type of byteswap passthru operation
+ *
+ * @CCP_PASSTHRU_BYTESWAP_NOOP: no byte swapping performed
+ * @CCP_PASSTHRU_BYTESWAP_32BIT: swap bytes within 32-bit words
+ * @CCP_PASSTHRU_BYTESWAP_256BIT: swap bytes within 256-bit words
+ */
+enum ccp_passthru_byteswap {
+       CCP_PASSTHRU_BYTESWAP_NOOP = 0,
+       CCP_PASSTHRU_BYTESWAP_32BIT,
+       CCP_PASSTHRU_BYTESWAP_256BIT,
+       CCP_PASSTHRU_BYTESWAP__LAST,
+};
+
+/**
+ * CCP passthru
+ */
+struct ccp_passthru {
+       phys_addr_t src_addr;
+       phys_addr_t dest_addr;
+       enum ccp_passthru_bitwise bit_mod;
+       enum ccp_passthru_byteswap byte_swap;
+       int len;
+       int dir;
+};
+
+/* CCP version 5: Union to define the function field (cmd_reg1/dword0) */
+union ccp_function {
+       struct {
+               uint16_t size:7;
+               uint16_t encrypt:1;
+               uint16_t mode:5;
+               uint16_t type:2;
+       } aes;
+       struct {
+               uint16_t size:7;
+               uint16_t encrypt:1;
+               uint16_t mode:5;
+               uint16_t type:2;
+       } des;
+       struct {
+               uint16_t size:7;
+               uint16_t encrypt:1;
+               uint16_t rsvd:5;
+               uint16_t type:2;
+       } aes_xts;
+       struct {
+               uint16_t rsvd1:10;
+               uint16_t type:4;
+               uint16_t rsvd2:1;
+       } sha;
+       struct {
+               uint16_t mode:3;
+               uint16_t size:12;
+       } rsa;
+       struct {
+               uint16_t byteswap:2;
+               uint16_t bitwise:3;
+               uint16_t reflect:2;
+               uint16_t rsvd:8;
+       } pt;
+       struct  {
+               uint16_t rsvd:13;
+       } zlib;
+       struct {
+               uint16_t size:10;
+               uint16_t type:2;
+               uint16_t mode:3;
+       } ecc;
+       uint16_t raw;
+};
+
+
 /**
  * descriptor for version 5 CPP commands
  * 8 32-bit words:
@@ -265,6 +385,18 @@ struct ccp_desc {
        struct dword7 dw7;
 };
 
+/**
+ * cmd id to follow order
+ */
+enum ccp_cmd_order {
+       CCP_CMD_CIPHER = 0,
+       CCP_CMD_AUTH,
+       CCP_CMD_CIPHER_HASH,
+       CCP_CMD_HASH_CIPHER,
+       CCP_CMD_COMBINED,
+       CCP_CMD_NOT_SUPPORTED,
+};
+
 static inline uint32_t
 low32_value(unsigned long addr)
 {
@@ -290,4 +422,21 @@ int ccp_dev_start(struct rte_cryptodev *dev);
  */
 int ccp_probe_devices(const struct rte_pci_id *ccp_id);
 
+/**
+ * allocate a ccp command queue
+ *
+ * @dev rte crypto device
+ * @param slot_req number of required
+ * @return allotted CCP queue on success otherwise NULL
+ */
+struct ccp_queue *ccp_allot_queue(struct rte_cryptodev *dev, int slot_req);
+
+/**
+ * read hwrng value
+ *
+ * @param trng_value data pointer to write RNG value
+ * @return 0 on success otherwise -1
+ */
+int ccp_read_hwrng(uint32_t *trng_value);
+
 #endif /* _CCP_DEV_H_ */