event/octeontx2: fix crypto adapter queue pair operations

[dpdk.git] / drivers / crypto / dpaa2_sec / dpaa2_sec_dpseci.c

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index afcd6bd..05b194c 100644 (file)
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2020 NXP
+ *   Copyright 2016-2021 NXP
  *
  */
 
@@ -1472,13 +1472,15 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
                        dpaa2_eqcr_size : nb_ops;
 
                for (loop = 0; loop < frames_to_send; loop++) {
-                       if ((*ops)->sym->m_src->seqn) {
-                        uint8_t dqrr_index = (*ops)->sym->m_src->seqn - 1;
-
-                        flags[loop] = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
-                        DPAA2_PER_LCORE_DQRR_SIZE--;
-                        DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
-                        (*ops)->sym->m_src->seqn = DPAA2_INVALID_MBUF_SEQN;
+                       if (*dpaa2_seqn((*ops)->sym->m_src)) {
+                               uint8_t dqrr_index =
+                                       *dpaa2_seqn((*ops)->sym->m_src) - 1;
+
+                               flags[loop] = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
+                               DPAA2_PER_LCORE_DQRR_SIZE--;
+                               DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
+                               *dpaa2_seqn((*ops)->sym->m_src) =
+                                       DPAA2_INVALID_MBUF_SEQN;
                        }
 
                        /*Clear the unused FD fields before sending*/
@@ -1840,7 +1842,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
        session->ctxt_type = DPAA2_SEC_CIPHER;
        session->cipher_key.data = rte_zmalloc(NULL, xform->cipher.key.length,
                        RTE_CACHE_LINE_SIZE);
-       if (session->cipher_key.data == NULL) {
+       if (session->cipher_key.data == NULL && xform->cipher.key.length > 0) {
                DPAA2_SEC_ERR("No Memory for cipher key");
                rte_free(priv);
                return -ENOMEM;
@@ -2132,10 +2134,28 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
                                           !session->dir,
                                           session->digest_length);
                break;
-       case RTE_CRYPTO_AUTH_AES_GMAC:
        case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+               authdata.algtype = OP_ALG_ALGSEL_AES;
+               authdata.algmode = OP_ALG_AAI_XCBC_MAC;
+               session->auth_alg = RTE_CRYPTO_AUTH_AES_XCBC_MAC;
+               bufsize = cnstr_shdsc_aes_mac(
+                                       priv->flc_desc[DESC_INITFINAL].desc,
+                                       1, 0, SHR_NEVER, &authdata,
+                                       !session->dir,
+                                       session->digest_length);
+               break;
        case RTE_CRYPTO_AUTH_AES_CMAC:
+               authdata.algtype = OP_ALG_ALGSEL_AES;
+               authdata.algmode = OP_ALG_AAI_CMAC;
+               session->auth_alg = RTE_CRYPTO_AUTH_AES_CMAC;
+               bufsize = cnstr_shdsc_aes_mac(
+                                          priv->flc_desc[DESC_INITFINAL].desc,
+                                          1, 0, SHR_NEVER, &authdata,
+                                          !session->dir,
+                                          session->digest_length);
+               break;
        case RTE_CRYPTO_AUTH_AES_CBC_MAC:
+       case RTE_CRYPTO_AUTH_AES_GMAC:
        case RTE_CRYPTO_AUTH_KASUMI_F9:
        case RTE_CRYPTO_AUTH_NULL:
                DPAA2_SEC_ERR("Crypto: Unsupported auth alg %un",
@@ -2404,6 +2424,17 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
                session->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC;
                break;
        case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+               authdata.algtype = OP_ALG_ALGSEL_AES;
+               authdata.algmode = OP_ALG_AAI_XCBC_MAC;
+               session->auth_alg = RTE_CRYPTO_AUTH_AES_XCBC_MAC;
+               break;
+       case RTE_CRYPTO_AUTH_AES_CMAC:
+               authdata.algtype = OP_ALG_ALGSEL_AES;
+               authdata.algmode = OP_ALG_AAI_CMAC;
+               session->auth_alg = RTE_CRYPTO_AUTH_AES_CMAC;
+               break;
+       case RTE_CRYPTO_AUTH_AES_CBC_MAC:
+       case RTE_CRYPTO_AUTH_AES_GMAC:
        case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
        case RTE_CRYPTO_AUTH_NULL:
        case RTE_CRYPTO_AUTH_SHA1:
@@ -2412,10 +2443,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_SHA224:
        case RTE_CRYPTO_AUTH_SHA384:
        case RTE_CRYPTO_AUTH_MD5:
-       case RTE_CRYPTO_AUTH_AES_GMAC:
        case RTE_CRYPTO_AUTH_KASUMI_F9:
-       case RTE_CRYPTO_AUTH_AES_CMAC:
-       case RTE_CRYPTO_AUTH_AES_CBC_MAC:
        case RTE_CRYPTO_AUTH_ZUC_EIA3:
                DPAA2_SEC_ERR("Crypto: Unsupported auth alg %u",
                              auth_xform->algo);
@@ -2748,14 +2776,18 @@ dpaa2_sec_ipsec_proto_init(struct rte_crypto_cipher_xform *cipher_xform,
                authdata->algtype = OP_PCL_IPSEC_HMAC_SHA2_512_256;
                authdata->algmode = OP_ALG_AAI_HMAC;
                break;
+       case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+               authdata->algtype = OP_PCL_IPSEC_AES_XCBC_MAC_96;
+               authdata->algmode = OP_ALG_AAI_XCBC_MAC;
+               break;
        case RTE_CRYPTO_AUTH_AES_CMAC:
                authdata->algtype = OP_PCL_IPSEC_AES_CMAC_96;
+               authdata->algmode = OP_ALG_AAI_CMAC;
                break;
        case RTE_CRYPTO_AUTH_NULL:
                authdata->algtype = OP_PCL_IPSEC_HMAC_NULL;
                break;
        case RTE_CRYPTO_AUTH_SHA224_HMAC:
-       case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
        case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
        case RTE_CRYPTO_AUTH_SHA1:
        case RTE_CRYPTO_AUTH_SHA256:
@@ -2818,12 +2850,6 @@ dpaa2_sec_ipsec_proto_init(struct rte_crypto_cipher_xform *cipher_xform,
        return 0;
 }
 
-#ifdef RTE_LIBRTE_SECURITY_TEST
-static uint8_t aes_cbc_iv[] = {
-       0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-       0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f };
-#endif
-
 static int
 dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
                            struct rte_security_session_conf *conf,
@@ -3714,7 +3740,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 
        ev->event_ptr = sec_fd_to_mbuf(fd);
        dqrr_index = qbman_get_dqrr_idx(dq);
-       crypto_op->sym->m_src->seqn = dqrr_index + 1;
+       *dpaa2_seqn(crypto_op->sym->m_src) = dqrr_index + 1;
        DPAA2_PER_LCORE_DQRR_SIZE++;
        DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
        DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src;