crypto/dpaa2_sec: fix OP storage for physical IOVA mode

[dpdk.git] / drivers / crypto / dpaa2_sec / dpaa2_sec_dpseci.c

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 784b96d..c484e36 100644 (file)
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -30,6 +30,9 @@
 #include "dpaa2_sec_priv.h"
 #include "dpaa2_sec_logs.h"
 
+/* Required types */
+typedef uint64_t       dma_addr_t;
+
 /* RTA header files */
 #include <hw/desc/ipsec.h>
 #include <hw/desc/algo.h>
@@ -119,7 +122,7 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,
                return -1;
        }
        memset(fle, 0, FLE_SG_MEM_SIZE);
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv);
 
        op_fle = fle + 1;
@@ -270,7 +273,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
                return -1;
        }
        memset(fle, 0, FLE_POOL_BUF_SIZE);
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
        fle = fle + 1;
        sge = fle + 2;
@@ -415,7 +418,7 @@ build_authenc_sg_fd(dpaa2_sec_session *sess,
                return -1;
        }
        memset(fle, 0, FLE_SG_MEM_SIZE);
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
 
        op_fle = fle + 1;
@@ -564,7 +567,7 @@ build_authenc_fd(dpaa2_sec_session *sess,
                return -1;
        }
        memset(fle, 0, FLE_POOL_BUF_SIZE);
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
        fle = fle + 1;
        sge = fle + 2;
@@ -694,7 +697,7 @@ static inline int build_auth_sg_fd(
        }
        memset(fle, 0, FLE_SG_MEM_SIZE);
        /* first FLE entry used to store mbuf and session ctxt */
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
        op_fle = fle + 1;
        ip_fle = fle + 2;
@@ -775,7 +778,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
         * to get the MBUF Addr from the previous FLE.
         * We can have a better approach to use the inline Mbuf
         */
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
        fle = fle + 1;
 
@@ -867,7 +870,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
        }
        memset(fle, 0, FLE_SG_MEM_SIZE);
        /* first FLE entry used to store mbuf and session ctxt */
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
 
        op_fle = fle + 1;
@@ -991,7 +994,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
         * to get the MBUF Addr from the previous FLE.
         * We can have a better approach to use the inline Mbuf
         */
-       DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
+       DPAA2_SET_FLE_ADDR(fle, (size_t)op);
        DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
        fle = fle + 1;
        sge = fle + 2;
@@ -1159,14 +1162,14 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
        qbman_eq_desc_set_response(&eqdesc, 0, 0);
        qbman_eq_desc_set_fq(&eqdesc, dpaa2_qp->tx_vq.fqid);
 
-       if (!DPAA2_PER_LCORE_SEC_DPIO) {
-               ret = dpaa2_affine_qbman_swp_sec();
+       if (!DPAA2_PER_LCORE_DPIO) {
+               ret = dpaa2_affine_qbman_swp();
                if (ret) {
                        DPAA2_SEC_ERR("Failure in affining portal");
                        return 0;
                }
        }
-       swp = DPAA2_PER_LCORE_SEC_PORTAL;
+       swp = DPAA2_PER_LCORE_PORTAL;
 
        while (nb_ops) {
                frames_to_send = (nb_ops >> 3) ? MAX_TX_RING_SLOTS : nb_ops;
@@ -1307,14 +1310,14 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops,
        const struct qbman_fd *fd;
        struct qbman_pull_desc pulldesc;
 
-       if (!DPAA2_PER_LCORE_SEC_DPIO) {
-               ret = dpaa2_affine_qbman_swp_sec();
+       if (!DPAA2_PER_LCORE_DPIO) {
+               ret = dpaa2_affine_qbman_swp();
                if (ret) {
                        DPAA2_SEC_ERR("Failure in affining portal");
                        return 0;
                }
        }
-       swp = DPAA2_PER_LCORE_SEC_PORTAL;
+       swp = DPAA2_PER_LCORE_PORTAL;
        dq_storage = dpaa2_qp->rx_vq.q_storage->dq_storage[0];
 
        qbman_pull_desc_clear(&pulldesc);
@@ -2916,8 +2919,8 @@ static struct rte_dpaa2_driver rte_dpaa2_sec_driver = {
 static struct cryptodev_driver dpaa2_sec_crypto_drv;
 
 RTE_PMD_REGISTER_DPAA2(CRYPTODEV_NAME_DPAA2_SEC_PMD, rte_dpaa2_sec_driver);
-RTE_PMD_REGISTER_CRYPTO_DRIVER(dpaa2_sec_crypto_drv, rte_dpaa2_sec_driver,
-               cryptodev_driver_id);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(dpaa2_sec_crypto_drv,
+               rte_dpaa2_sec_driver.driver, cryptodev_driver_id);
 
 RTE_INIT(dpaa2_sec_init_log);
 static void