crypto/qat: refactor asym algorithm macros and logs

[dpdk.git] / drivers / crypto / dpaa2_sec / dpaa2_sec_priv.h

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
index a8f9440..63f4c64 100644 (file)
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016,2020-2021 NXP
+ *   Copyright 2016,2020-2022 NXP
  *
  */
 
@@ -31,17 +31,19 @@ extern uint8_t cryptodev_driver_id;
 struct dpaa2_sec_dev_private {
        void *mc_portal; /**< MC Portal for configuring this device */
        void *hw; /**< Hardware handle for this device.Used by NADK framework */
-       struct rte_mempool *fle_pool; /* per device memory pool for FLE */
        int32_t hw_id; /**< An unique ID of this device instance */
        int32_t vfio_fd; /**< File descriptor received via VFIO */
        uint16_t token; /**< Token required by DPxxx objects */
        unsigned int max_nb_queue_pairs;
        /**< Max number of queue pairs supported by device */
+       uint8_t en_ordered;
+       uint8_t en_loose_ordered;
 };
 
 struct dpaa2_sec_qp {
        struct dpaa2_queue rx_vq;
        struct dpaa2_queue tx_vq;
+       struct rte_mempool *fle_pool; /* per device memory pool for FLE */
 };
 
 enum shr_desc_type {
@@ -125,7 +127,6 @@ struct sec_flc_desc {
 };
 
 struct ctxt_priv {
-       struct rte_mempool *fle_pool; /* per device memory pool for FLE */
        struct sec_flc_desc flc_desc[0];
 };