#include "otx2_common.h"
#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_capabilities.h"
#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
+#include "otx2_cryptodev_sec.h"
#include "otx2_dev.h"
/* CPT common headers */
#include "cpt_common.h"
#include "cpt_pmd_logs.h"
-int otx2_cpt_logtype;
-
uint8_t otx2_cryptodev_driver_id;
static struct rte_pci_id pci_id_cpt_table[] = {
CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
+ ret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps);
+ if (ret) {
+ CPT_LOG_ERR("Could not determine hardware capabilities");
+ goto otx2_dev_fini;
+ }
+
+ otx2_crypto_capabilities_init(vf->hw_caps);
+ otx2_crypto_sec_capabilities_init(vf->hw_caps);
+
+ /* Create security ctx */
+ ret = otx2_crypto_sec_ctx_create(dev);
+ if (ret)
+ goto otx2_dev_fini;
+
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_HW_ACCELERATED |
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT |
- RTE_CRYPTODEV_FF_SYM_SESSIONLESS;
+ RTE_CRYPTODEV_FF_SYM_SESSIONLESS |
+ RTE_CRYPTODEV_FF_SECURITY;
return 0;
if (dev == NULL)
return -ENODEV;
+ /* Destroy security ctx */
+ otx2_crypto_sec_ctx_destroy(dev);
+
return rte_cryptodev_pmd_destroy(dev);
}
static struct cryptodev_driver otx2_cryptodev_drv;
-RTE_INIT(otx2_cpt_init_log);
RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);
RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);
RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_OCTEONTX2_PMD, "vfio-pci");
RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,
otx2_cryptodev_driver_id);
-
-RTE_INIT(otx2_cpt_init_log)
-{
- /* Bus level logs */
- otx2_cpt_logtype = rte_log_register("pmd.crypto.octeontx2");
- if (otx2_cpt_logtype >= 0)
- rte_log_set_level(otx2_cpt_logtype, RTE_LOG_NOTICE);
-}
+RTE_LOG_REGISTER(otx2_cpt_logtype, pmd.crypto.octeontx2, NOTICE);