#include "cpt_common.h"
#include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
#include "otx2_dev.h"
+#include "otx2_cryptodev_qp.h"
/* CPT instruction queue length */
#define OTX2_CPT_IQ_LEN 8200
#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3)
#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
+#define OTX2_CPT_AF_LF_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
-#define OTX2_CPT_LF_BAR2(vf, q_id) \
+#define OTX2_CPT_LF_BAR2(vf, blk_addr, q_id) \
((vf)->otx2_dev.bar2 + \
- ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
+ ((blk_addr << 20) | ((q_id) << 12)))
#define OTX2_CPT_QUEUE_HI_PRIO 0x1
} s;
};
+union otx2_cpt_af_lf_ctl2 {
+ uint64_t u;
+ struct {
+ uint64_t exe_no_swap : 1;
+ uint64_t exe_ldwb : 1;
+ uint64_t reserved_2_31 : 30;
+ uint64_t sso_pf_func : 16;
+ uint64_t nix_pf_func : 16;
+ } s;
+};
+
union otx2_cpt_lf_q_grp_ptr {
uint64_t u;
struct {
} s;
};
-struct otx2_cpt_qp {
- uint32_t id;
- /**< Queue pair id */
- uintptr_t base;
- /**< Base address where BAR is mapped */
- void *lmtline;
- /**< Address of LMTLINE */
- rte_iova_t lf_nq_reg;
- /**< LF enqueue register address */
- struct pending_queue pend_q;
- /**< Pending queue */
- struct rte_mempool *sess_mp;
- /**< Session mempool */
- struct rte_mempool *sess_mp_priv;
- /**< Session private data mempool */
- struct cpt_qp_meta_info meta_info;
- /**< Metabuf info required to support operations on the queue pair */
- rte_iova_t iq_dma_addr;
- /**< Instruction queue address */
+/*
+ * Enumeration cpt_9x_comp_e
+ *
+ * CPT 9X Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+enum cpt_9x_comp_e {
+ CPT_9X_COMP_E_NOTDONE = 0x00,
+ CPT_9X_COMP_E_GOOD = 0x01,
+ CPT_9X_COMP_E_FAULT = 0x02,
+ CPT_9X_COMP_E_HWERR = 0x04,
+ CPT_9X_COMP_E_INSTERR = 0x05,
+ CPT_9X_COMP_E_LAST_ENTRY = 0x06
};
void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);