baseband/acc100: introduce PMD for ACC100

[dpdk.git] / drivers / crypto / octeontx2 / otx2_cryptodev_mbox.c

diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index b54e407..6028439 100644 (file)
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -2,14 +2,39 @@
  * Copyright (C) 2019 Marvell International Ltd.
  */
 #include <rte_cryptodev.h>
+#include <rte_ethdev.h>
 
 #include "otx2_cryptodev.h"
+#include "otx2_cryptodev_hw_access.h"
 #include "otx2_cryptodev_mbox.h"
 #include "otx2_dev.h"
+#include "otx2_ethdev.h"
+#include "otx2_sec_idev.h"
 #include "otx2_mbox.h"
 
 #include "cpt_pmd_logs.h"
 
+int
+otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,
+                             union cpt_eng_caps *hw_caps)
+{
+       struct otx2_cpt_vf *vf = dev->data->dev_private;
+       struct otx2_dev *otx2_dev = &vf->otx2_dev;
+       struct cpt_caps_rsp_msg *rsp;
+       int ret;
+
+       otx2_mbox_alloc_msg_cpt_caps_get(otx2_dev->mbox);
+
+       ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
+       if (ret)
+               return -EIO;
+
+       memcpy(hw_caps, rsp->eng_caps,
+               sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
+
+       return 0;
+}
+
 int
 otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
                              uint16_t *nb_queues)
@@ -173,3 +198,53 @@ otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
 
        return otx2_cpt_send_mbox_msg(vf);
 }
+
+int
+otx2_cpt_inline_init(const struct rte_cryptodev *dev)
+{
+       struct otx2_cpt_vf *vf = dev->data->dev_private;
+       struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+       struct cpt_rx_inline_lf_cfg_msg *msg;
+       int ret;
+
+       msg = otx2_mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);
+       msg->sso_pf_func = otx2_sso_pf_func_get();
+
+       otx2_mbox_msg_send(mbox, 0);
+       ret = otx2_mbox_process(mbox);
+       if (ret < 0)
+               return -EIO;
+
+       return 0;
+}
+
+int
+otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp,
+                       uint16_t port_id)
+{
+       struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];
+       struct otx2_cpt_vf *vf = dev->data->dev_private;
+       struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+       struct cpt_inline_ipsec_cfg_msg *msg;
+       struct otx2_eth_dev *otx2_eth_dev;
+       int ret;
+
+       if (!otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
+               return -EINVAL;
+
+       otx2_eth_dev = otx2_eth_pmd_priv(eth_dev);
+
+       msg = otx2_mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);
+       msg->dir = CPT_INLINE_OUTBOUND;
+       msg->enable = 1;
+       msg->slot = qp->id;
+
+       msg->nix_pf_func = otx2_eth_dev->pf_func;
+
+       otx2_mbox_msg_send(mbox, 0);
+       ret = otx2_mbox_process(mbox);
+       if (ret < 0)
+               return -EIO;
+
+       return 0;
+}