cryptodev: pass IV as offset
[dpdk.git] / drivers / crypto / qat / qat_crypto.c
index 0a14c2d..b7f891b 100644 (file)
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -60,6 +60,7 @@
 #include <rte_spinlock.h>
 #include <rte_hexdump.h>
 #include <rte_crypto_sym.h>
+#include <rte_cryptodev_pci.h>
 #include <openssl/evp.h>
 
 #include "qat_logs.h"
@@ -641,7 +642,8 @@ qat_bpicipher_preprocess(struct qat_session *ctx,
                        iv = last_block - block_len;
                else
                        /* runt block, i.e. less than one full block */
-                       iv = sym_op->cipher.iv.data;
+                       iv = rte_crypto_op_ctod_offset(op, uint8_t *,
+                                       sym_op->cipher.iv.offset);
 
 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
                rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
@@ -696,7 +698,8 @@ qat_bpicipher_postprocess(struct qat_session *ctx,
                        iv = dst - block_len;
                else
                        /* runt block, i.e. less than one full block */
-                       iv = sym_op->cipher.iv.data;
+                       iv = rte_crypto_op_ctod_offset(op, uint8_t *,
+                                       sym_op->cipher.iv.offset);
 
 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
                rte_hexdump(stdout, "BPI: src before post-process:", last_block,
@@ -897,6 +900,7 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
        uint32_t min_ofs = 0;
        uint64_t src_buf_start = 0, dst_buf_start = 0;
        uint8_t do_sgl = 0;
+       uint8_t *iv_ptr;
 
 
 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
@@ -907,7 +911,7 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
                return -EINVAL;
        }
 #endif
-       if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
+       if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
                PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
                                " requests, op (%p) is sessionless.", op);
                return -EINVAL;
@@ -970,6 +974,8 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
                        cipher_ofs = op->sym->cipher.data.offset;
                }
 
+               iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
+                                       op->sym->cipher.iv.offset);
                /* copy IV into request if it fits */
                /*
                 * If IV length is zero do not copy anything but still
@@ -980,14 +986,15 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
                        if (op->sym->cipher.iv.length <=
                                        sizeof(cipher_param->u.cipher_IV_array)) {
                                rte_memcpy(cipher_param->u.cipher_IV_array,
-                                               op->sym->cipher.iv.data,
+                                               iv_ptr,
                                                op->sym->cipher.iv.length);
                        } else {
                                ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
                                                qat_req->comn_hdr.serv_specif_flags,
                                                ICP_QAT_FW_CIPH_IV_64BIT_PTR);
                                cipher_param->u.s.cipher_IV_ptr =
-                                               op->sym->cipher.iv.phys_addr;
+                                               rte_crypto_op_ctophys_offset(op,
+                                                       op->sym->cipher.iv.offset);
                        }
                }
                min_ofs = cipher_ofs;
@@ -1146,7 +1153,7 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
                        ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
                if (op->sym->cipher.iv.length == 12) {
                        /*
-                        * For GCM a 12 bit IV is allowed,
+                        * For GCM a 12 byte IV is allowed,
                         * but we need to inform the f/w
                         */
                        ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
@@ -1178,12 +1185,16 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
        rte_hexdump(stdout, "src_data:",
                        rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
                        rte_pktmbuf_data_len(op->sym->m_src));
-       rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
-                       op->sym->cipher.iv.length);
-       rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
-                       op->sym->auth.digest.length);
-       rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
-                       op->sym->auth.aad.length);
+       if (do_cipher)
+               rte_hexdump(stdout, "iv:", iv_ptr,
+                               op->sym->cipher.iv.length);
+
+       if (do_auth) {
+               rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
+                               op->sym->auth.digest.length);
+               rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
+                               op->sym->auth.aad.length);
+       }
 #endif
        return 0;
 }