net/enic: fix TSO for packets greater than 9208 bytes

[dpdk.git] / drivers / crypto / qat / qat_crypto.h

diff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h
index d78957c..c64d775 100644 (file)
--- a/drivers/crypto/qat/qat_crypto.h
+++ b/drivers/crypto/qat/qat_crypto.h
@@ -52,6 +52,10 @@
 
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
+#define QAT_CSR_TAIL_WRITE_THRESH 32U
+/* number of requests to accumulate before writing tail CSR */
+#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
+/* number of inflights below which no tail write coalescing should occur */
 
 struct qat_session;
 
@@ -66,7 +70,7 @@ enum qat_device_gen {
 struct qat_queue {
        char            memz_name[RTE_MEMZONE_NAMESIZE];
        void            *base_addr;             /* Base address */
-       phys_addr_t     base_phys_addr;         /* Queue physical address */
+       rte_iova_t      base_phys_addr;         /* Queue physical address */
        uint32_t        head;                   /* Shadow copy of the head */
        uint32_t        tail;                   /* Shadow copy of the tail */
        uint32_t        modulo;
@@ -77,8 +81,11 @@ struct qat_queue {
        uint8_t         hw_queue_number;
        /* HW queue aka ring offset on bundle */
        uint32_t        csr_head;               /* last written head value */
+       uint32_t        csr_tail;               /* last written tail value */
        uint16_t        nb_processed_responses;
        /* number of responses processed since last CSR head write */
+       uint16_t        nb_pending_requests;
+       /* number of requests pending since last CSR tail write */
 };
 
 struct qat_qp {