#include "dpaa_qdma.h"
#include "dpaa_qdma_logs.h"
+static inline void
+qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)
+{
+ ccdf->addr_hi = upper_32_bits(addr);
+ ccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr));
+}
+
+static inline u64
+qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)
+{
+ return ccdf->cfg8b_w1 & 0xff;
+}
+
+static inline int
+qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)
+{
+ return (rte_le_to_cpu_32(ccdf->cfg) & QDMA_CCDF_MASK)
+ >> QDMA_CCDF_OFFSET;
+}
+
+static inline void
+qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)
+{
+ ccdf->cfg = rte_cpu_to_le_32(QDMA_CCDF_FOTMAT | offset);
+}
+
+static inline int
+qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)
+{
+ return (rte_le_to_cpu_32(ccdf->status) & QDMA_CCDF_MASK)
+ >> QDMA_CCDF_STATUS;
+}
+
+static inline void
+qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)
+{
+ ccdf->status = rte_cpu_to_le_32(QDMA_CCDF_SER | status);
+}
+
+static inline void
+qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)
+{
+ csgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK);
+}
+
+static inline void
+qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)
+{
+ csgf->cfg = rte_cpu_to_le_32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));
+}
+
static inline int
ilog2(int x)
{
QDMA_OUT(addr, val);
}
+static u32
+qdma_readl_be(void *addr)
+{
+ return QDMA_IN_BE(addr);
+}
+
+static void
+qdma_writel_be(u32 val, void *addr)
+{
+ QDMA_OUT_BE(addr, val);
+}
+
static void
*dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr)
{
fsl_qdma->desc_allocated--;
}
+static void
+fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
+ dma_addr_t dst, dma_addr_t src, u32 len)
+{
+ struct fsl_qdma_format *csgf_src, *csgf_dest;
+
+ /* Note: command table (fsl_comp->virt_addr) is getting filled
+ * directly in cmd descriptors of queues while enqueuing the descriptor
+ * please refer fsl_qdma_enqueue_desc
+ * frame list table (virt_addr) + 1) and source,
+ * destination descriptor table
+ * (fsl_comp->desc_virt_addr and fsl_comp->desc_virt_addr+1) move to
+ * the control path to fsl_qdma_pre_request_enqueue_comp_sd_desc
+ */
+ csgf_src = (struct fsl_qdma_format *)fsl_comp->virt_addr + 2;
+ csgf_dest = (struct fsl_qdma_format *)fsl_comp->virt_addr + 3;
+
+ /* Status notification is enqueued to status queue. */
+ qdma_desc_addr_set64(csgf_src, src);
+ qdma_csgf_set_len(csgf_src, len);
+ qdma_desc_addr_set64(csgf_dest, dst);
+ qdma_csgf_set_len(csgf_dest, len);
+ /* This entry is the last entry. */
+ qdma_csgf_set_f(csgf_dest, len);
+}
+
+/*
+ * Pre-request command descriptor and compound S/G for enqueue.
+ */
+static int
+fsl_qdma_pre_request_enqueue_comp_sd_desc(
+ struct fsl_qdma_queue *queue,
+ int size, int aligned)
+{
+ struct fsl_qdma_comp *comp_temp, *_comp_temp;
+ struct fsl_qdma_sdf *sdf;
+ struct fsl_qdma_ddf *ddf;
+ struct fsl_qdma_format *csgf_desc;
+ int i;
+
+ for (i = 0; i < (int)(queue->n_cq + COMMAND_QUEUE_OVERFLOW); i++) {
+ comp_temp = rte_zmalloc("qdma: comp temp",
+ sizeof(*comp_temp), 0);
+ if (!comp_temp)
+ return -ENOMEM;
+
+ comp_temp->virt_addr =
+ dma_pool_alloc(size, aligned, &comp_temp->bus_addr);
+ if (!comp_temp->virt_addr) {
+ rte_free(comp_temp);
+ goto fail;
+ }
+
+ comp_temp->desc_virt_addr =
+ dma_pool_alloc(size, aligned, &comp_temp->desc_bus_addr);
+ if (!comp_temp->desc_virt_addr) {
+ rte_free(comp_temp->virt_addr);
+ rte_free(comp_temp);
+ goto fail;
+ }
+
+ memset(comp_temp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
+ memset(comp_temp->desc_virt_addr, 0,
+ FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
+
+ csgf_desc = (struct fsl_qdma_format *)comp_temp->virt_addr + 1;
+ sdf = (struct fsl_qdma_sdf *)comp_temp->desc_virt_addr;
+ ddf = (struct fsl_qdma_ddf *)comp_temp->desc_virt_addr + 1;
+ /* Compound Command Descriptor(Frame List Table) */
+ qdma_desc_addr_set64(csgf_desc, comp_temp->desc_bus_addr);
+ /* It must be 32 as Compound S/G Descriptor */
+ qdma_csgf_set_len(csgf_desc, 32);
+ /* Descriptor Buffer */
+ sdf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ ddf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ ddf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_LWC <<
+ FSL_QDMA_CMD_LWC_OFFSET);
+
+ list_add_tail(&comp_temp->list, &queue->comp_free);
+ }
+
+ return 0;
+
+fail:
+ list_for_each_entry_safe(comp_temp, _comp_temp,
+ &queue->comp_free, list) {
+ list_del(&comp_temp->list);
+ rte_free(comp_temp->virt_addr);
+ rte_free(comp_temp->desc_virt_addr);
+ rte_free(comp_temp);
+ }
+
+ return -ENOMEM;
+}
+
+/*
+ * Request a command descriptor for enqueue.
+ */
+static struct fsl_qdma_comp *
+fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
+{
+ struct fsl_qdma_queue *queue = fsl_chan->queue;
+ struct fsl_qdma_comp *comp_temp;
+
+ if (!list_empty(&queue->comp_free)) {
+ comp_temp = list_first_entry(&queue->comp_free,
+ struct fsl_qdma_comp,
+ list);
+ list_del(&comp_temp->list);
+ return comp_temp;
+ }
+
+ return NULL;
+}
+
static struct fsl_qdma_queue
*fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma)
{
queue_temp->count = 0;
queue_temp->pending = 0;
queue_temp->virt_head = queue_temp->cq;
-
+ queue_temp->stats = (struct rte_dma_stats){0};
}
}
return queue_head;
return 0;
}
+static int
+fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
+ void *block, int id, const uint16_t nb_cpls,
+ uint16_t *last_idx,
+ enum rte_dma_status_code *status)
+{
+ struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
+ struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
+ struct fsl_qdma_queue *temp_queue;
+ struct fsl_qdma_format *status_addr;
+ struct fsl_qdma_comp *fsl_comp = NULL;
+ u32 reg, i;
+ int count = 0;
+
+ while (count < nb_cpls) {
+ reg = qdma_readl_be(block + FSL_QDMA_BSQSR);
+ if (reg & FSL_QDMA_BSQSR_QE_BE)
+ return count;
+
+ status_addr = fsl_status->virt_head;
+
+ i = qdma_ccdf_get_queue(status_addr) +
+ id * fsl_qdma->n_queues;
+ temp_queue = fsl_queue + i;
+ fsl_comp = list_first_entry(&temp_queue->comp_used,
+ struct fsl_qdma_comp,
+ list);
+ list_del(&fsl_comp->list);
+
+ reg = qdma_readl_be(block + FSL_QDMA_BSQMR);
+ reg |= FSL_QDMA_BSQMR_DI_BE;
+
+ qdma_desc_addr_set64(status_addr, 0x0);
+ fsl_status->virt_head++;
+ if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
+ fsl_status->virt_head = fsl_status->cq;
+ qdma_writel_be(reg, block + FSL_QDMA_BSQMR);
+ *last_idx = fsl_comp->index;
+ if (status != NULL)
+ status[count] = RTE_DMA_STATUS_SUCCESSFUL;
+
+ list_add_tail(&fsl_comp->list, &temp_queue->comp_free);
+ count++;
+
+ }
+ return count;
+}
+
static int
fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
{
return 0;
}
+static void *
+fsl_qdma_prep_memcpy(void *fsl_chan, dma_addr_t dst,
+ dma_addr_t src, size_t len,
+ void *call_back,
+ void *param)
+{
+ struct fsl_qdma_comp *fsl_comp;
+
+ fsl_comp =
+ fsl_qdma_request_enqueue_desc((struct fsl_qdma_chan *)fsl_chan);
+ if (!fsl_comp)
+ return NULL;
+
+ fsl_comp->qchan = fsl_chan;
+ fsl_comp->call_back_func = call_back;
+ fsl_comp->params = param;
+
+ fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);
+ return (void *)fsl_comp;
+}
+
+static int
+fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan,
+ struct fsl_qdma_comp *fsl_comp,
+ uint64_t flags)
+{
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+ void *block = fsl_queue->block_base;
+ struct fsl_qdma_format *ccdf;
+ u32 reg;
+
+ /* retrieve and store the register value in big endian
+ * to avoid bits swap
+ */
+ reg = qdma_readl_be(block +
+ FSL_QDMA_BCQSR(fsl_queue->id));
+ if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE))
+ return -1;
+
+ /* filling descriptor command table */
+ ccdf = (struct fsl_qdma_format *)fsl_queue->virt_head;
+ qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
+ qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp->virt_addr));
+ qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr));
+ fsl_comp->index = fsl_queue->virt_head - fsl_queue->cq;
+ fsl_queue->virt_head++;
+
+ if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
+ fsl_queue->virt_head = fsl_queue->cq;
+
+ list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
+
+ if (flags == RTE_DMA_OP_FLAG_SUBMIT) {
+ reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));
+ reg |= FSL_QDMA_BCQMR_EI_BE;
+ qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));
+ fsl_queue->stats.submitted++;
+ } else {
+ fsl_queue->pending++;
+ }
+ return fsl_comp->index;
+}
+
+static int
+fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan)
+{
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+ struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
+ int ret;
+
+ if (fsl_queue->count++)
+ goto finally;
+
+ INIT_LIST_HEAD(&fsl_queue->comp_free);
+ INIT_LIST_HEAD(&fsl_queue->comp_used);
+
+ ret = fsl_qdma_pre_request_enqueue_comp_sd_desc(fsl_queue,
+ FSL_QDMA_COMMAND_BUFFER_SIZE, 64);
+ if (ret) {
+ DPAA_QDMA_ERR(
+ "failed to alloc dma buffer for comp descriptor\n");
+ goto exit;
+ }
+
+finally:
+ return fsl_qdma->desc_allocated++;
+
+exit:
+ return -ENOMEM;
+}
+
+static int
+dpaa_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info,
+ uint32_t info_sz)
+{
+#define DPAADMA_MAX_DESC 64
+#define DPAADMA_MIN_DESC 64
+
+ RTE_SET_USED(dev);
+ RTE_SET_USED(info_sz);
+
+ dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
+ RTE_DMA_CAPA_MEM_TO_DEV |
+ RTE_DMA_CAPA_DEV_TO_DEV |
+ RTE_DMA_CAPA_DEV_TO_MEM |
+ RTE_DMA_CAPA_SILENT |
+ RTE_DMA_CAPA_OPS_COPY;
+ dev_info->max_vchans = 1;
+ dev_info->max_desc = DPAADMA_MAX_DESC;
+ dev_info->min_desc = DPAADMA_MIN_DESC;
+
+ return 0;
+}
+
+static int
+dpaa_get_channel(struct fsl_qdma_engine *fsl_qdma, uint16_t vchan)
+{
+ u32 i, start, end;
+ int ret;
+
+ start = fsl_qdma->free_block_id * QDMA_QUEUES;
+ fsl_qdma->free_block_id++;
+
+ end = start + 1;
+ for (i = start; i < end; i++) {
+ struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
+
+ if (fsl_chan->free) {
+ fsl_chan->free = false;
+ ret = fsl_qdma_alloc_chan_resources(fsl_chan);
+ if (ret)
+ return ret;
+
+ fsl_qdma->vchan_map[vchan] = i;
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
static void
dma_release(void *fsl_chan)
{
fsl_qdma_free_chan_resources((struct fsl_qdma_chan *)fsl_chan);
}
+static int
+dpaa_qdma_configure(__rte_unused struct rte_dma_dev *dmadev,
+ __rte_unused const struct rte_dma_conf *dev_conf,
+ __rte_unused uint32_t conf_sz)
+{
+ return 0;
+}
+
+static int
+dpaa_qdma_start(__rte_unused struct rte_dma_dev *dev)
+{
+ return 0;
+}
+
+static int
+dpaa_qdma_close(__rte_unused struct rte_dma_dev *dev)
+{
+ return 0;
+}
+
+static int
+dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev,
+ uint16_t vchan,
+ __rte_unused const struct rte_dma_vchan_conf *conf,
+ __rte_unused uint32_t conf_sz)
+{
+ struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private;
+
+ return dpaa_get_channel(fsl_qdma, vchan);
+}
+
+static int
+dpaa_qdma_submit(void *dev_private, uint16_t vchan)
+{
+ struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;
+ struct fsl_qdma_chan *fsl_chan =
+ &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+ void *block = fsl_queue->block_base;
+ u32 reg;
+
+ while (fsl_queue->pending) {
+ reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));
+ reg |= FSL_QDMA_BCQMR_EI_BE;
+ qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));
+ fsl_queue->pending--;
+ fsl_queue->stats.submitted++;
+ }
+
+ return 0;
+}
+
+static int
+dpaa_qdma_enqueue(void *dev_private, uint16_t vchan,
+ rte_iova_t src, rte_iova_t dst,
+ uint32_t length, uint64_t flags)
+{
+ struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;
+ struct fsl_qdma_chan *fsl_chan =
+ &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
+ int ret;
+
+ void *fsl_comp = NULL;
+
+ fsl_comp = fsl_qdma_prep_memcpy(fsl_chan,
+ (dma_addr_t)dst, (dma_addr_t)src,
+ length, NULL, NULL);
+ if (!fsl_comp) {
+ DPAA_QDMA_DP_DEBUG("fsl_comp is NULL\n");
+ return -1;
+ }
+ ret = fsl_qdma_enqueue_desc(fsl_chan, fsl_comp, flags);
+
+ return ret;
+}
+
+static uint16_t
+dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan,
+ const uint16_t nb_cpls, uint16_t *last_idx,
+ enum rte_dma_status_code *st)
+{
+ struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;
+ int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES);
+ void *block;
+ int intr;
+ void *status = fsl_qdma->status_base;
+ struct fsl_qdma_chan *fsl_chan =
+ &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+
+ intr = qdma_readl_be(status + FSL_QDMA_DEDR);
+ if (intr) {
+ DPAA_QDMA_ERR("DMA transaction error! %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW0R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW1R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW2R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW3R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFQIDR);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECBR);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr);
+ qdma_writel(0xffffffff,
+ status + FSL_QDMA_DEDR);
+ intr = qdma_readl(status + FSL_QDMA_DEDR);
+ fsl_queue->stats.errors++;
+ }
+
+ block = fsl_qdma->block_base +
+ FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
+
+ intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls,
+ last_idx, st);
+ fsl_queue->stats.completed += intr;
+
+ return intr;
+}
+
+
+static uint16_t
+dpaa_qdma_dequeue(void *dev_private,
+ uint16_t vchan, const uint16_t nb_cpls,
+ uint16_t *last_idx, bool *has_error)
+{
+ struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;
+ int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES);
+ void *block;
+ int intr;
+ void *status = fsl_qdma->status_base;
+ struct fsl_qdma_chan *fsl_chan =
+ &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+
+ intr = qdma_readl_be(status + FSL_QDMA_DEDR);
+ if (intr) {
+ DPAA_QDMA_ERR("DMA transaction error! %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW0R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW1R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW2R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFDW3R);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECFQIDR);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr);
+ intr = qdma_readl(status + FSL_QDMA_DECBR);
+ DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr);
+ qdma_writel(0xffffffff,
+ status + FSL_QDMA_DEDR);
+ intr = qdma_readl(status + FSL_QDMA_DEDR);
+ *has_error = true;
+ fsl_queue->stats.errors++;
+ }
+
+ block = fsl_qdma->block_base +
+ FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
+
+ intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls,
+ last_idx, NULL);
+ fsl_queue->stats.completed += intr;
+
+ return intr;
+}
+
+static int
+dpaa_qdma_stats_get(const struct rte_dma_dev *dmadev, uint16_t vchan,
+ struct rte_dma_stats *rte_stats, uint32_t size)
+{
+ struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private;
+ struct fsl_qdma_chan *fsl_chan =
+ &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+ struct rte_dma_stats *stats = &fsl_queue->stats;
+
+ if (size < sizeof(rte_stats))
+ return -EINVAL;
+ if (rte_stats == NULL)
+ return -EINVAL;
+
+ *rte_stats = *stats;
+
+ return 0;
+}
+
+static int
+dpaa_qdma_stats_reset(struct rte_dma_dev *dmadev, uint16_t vchan)
+{
+ struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private;
+ struct fsl_qdma_chan *fsl_chan =
+ &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
+ struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
+
+ fsl_queue->stats = (struct rte_dma_stats){0};
+
+ return 0;
+}
+
+static struct rte_dma_dev_ops dpaa_qdma_ops = {
+ .dev_info_get = dpaa_info_get,
+ .dev_configure = dpaa_qdma_configure,
+ .dev_start = dpaa_qdma_start,
+ .dev_close = dpaa_qdma_close,
+ .vchan_setup = dpaa_qdma_queue_setup,
+ .stats_get = dpaa_qdma_stats_get,
+ .stats_reset = dpaa_qdma_stats_reset,
+};
+
static int
dpaa_qdma_init(struct rte_dma_dev *dmadev)
{
}
dpaa_dev->dmadev = dmadev;
+ dmadev->dev_ops = &dpaa_qdma_ops;
+ dmadev->device = &dpaa_dev->device;
+ dmadev->fp_obj->dev_private = dmadev->data->dev_private;
+ dmadev->fp_obj->copy = dpaa_qdma_enqueue;
+ dmadev->fp_obj->submit = dpaa_qdma_submit;
+ dmadev->fp_obj->completed = dpaa_qdma_dequeue;
+ dmadev->fp_obj->completed_status = dpaa_qdma_dequeue_status;
/* Invoke PMD device initialization function */
ret = dpaa_qdma_init(dmadev);
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