#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id) (0x800 + \
(queue_id) * 0x20)
#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B 16
+#define HISI_DMA_HIP09_DUMP_REGION_A_START_REG 0x0
+#define HISI_DMA_HIP09_DUMP_REGION_A_END_REG 0x368
+#define HISI_DMA_HIP09_DUMP_REGION_B_START_REG 0x800
+#define HISI_DMA_HIP09_DUMP_REGION_B_END_REG 0xA08
+#define HISI_DMA_HIP09_DUMP_REGION_C_START_REG 0x1800
+#define HISI_DMA_HIP09_DUMP_REGION_C_END_REG 0x1A4C
+#define HISI_DMA_HIP09_DUMP_REGION_D_START_REG 0x1C00
+#define HISI_DMA_HIP09_DUMP_REGION_D_END_REG 0x1CC4
/**
* In fact, there are multiple states, but it need to pay attention to
uint64_t submitted;
uint64_t completed;
uint64_t errors;
+ uint64_t qfulls;
/**
* The following fields are not accessed in the I/O path, so they are