common/mlx5: fix device list operations concurrency
[dpdk.git] / drivers / event / cnxk / cn10k_eventdev.c
index f14a3ed..8af273a 100644 (file)
@@ -316,6 +316,20 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 #undef R
        };
 
+       const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
        const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
        [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
@@ -345,6 +359,21 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 #undef R
                };
 
+       const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t
+               sso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,
+                       NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
        /* Tx modes */
        const event_tx_adapter_enqueue
                sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
@@ -377,6 +406,12 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                        CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
                                               sso_hws_deq_tmo_seg_burst);
                }
+               if (dev->is_ca_internal_port) {
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                              sso_hws_deq_ca_seg);
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
+                                              sso_hws_deq_ca_seg_burst);
+               }
        } else {
                CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
                CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
@@ -387,7 +422,14 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                        CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
                                               sso_hws_deq_tmo_burst);
                }
+               if (dev->is_ca_internal_port) {
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                              sso_hws_deq_ca);
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
+                                              sso_hws_deq_ca_burst);
+               }
        }
+       event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 
        if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
                CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
@@ -773,6 +815,49 @@ cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
        return cn10k_sso_updt_tx_adptr_data(event_dev);
 }
 
+static int
+cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
+                             const struct rte_cryptodev *cdev, uint32_t *caps)
+{
+       CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
+       CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
+
+       *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
+               RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
+
+       return 0;
+}
+
+static int
+cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
+                           const struct rte_cryptodev *cdev,
+                           int32_t queue_pair_id,
+                           const struct rte_event *event)
+{
+       struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+
+       RTE_SET_USED(event);
+
+       CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
+       CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
+
+       dev->is_ca_internal_port = 1;
+       cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
+
+       return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
+}
+
+static int
+cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
+                           const struct rte_cryptodev *cdev,
+                           int32_t queue_pair_id)
+{
+       CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
+       CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
+
+       return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
+}
+
 static struct rte_eventdev_ops cn10k_sso_dev_ops = {
        .dev_infos_get = cn10k_sso_info_get,
        .dev_configure = cn10k_sso_dev_configure,
@@ -802,6 +887,10 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = {
 
        .timer_adapter_caps_get = cnxk_tim_caps_get,
 
+       .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
+       .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
+       .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
+
        .dump = cnxk_sso_dump,
        .dev_start = cn10k_sso_start,
        .dev_stop = cn10k_sso_stop,