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common/cnxk: add new PCI IDs to supported devices
[dpdk.git] / drivers / event / cnxk / cn9k_eventdev.c
diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c
index c73d81c..d757da7 100644 (file)
--- a/drivers/event/cnxk/cn9k_eventdev.c
+++ b/drivers/event/cnxk/cn9k_eventdev.c
@@ -10,7 +10,8 @@
 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
 
 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                            \
-       (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]  \
+       (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]    \
+                        [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]  \
                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]      \
                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]    \
@@ -18,8 +19,8 @@
                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
 
 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                            \
-       (enq_op =                                                              \
-                enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]       \
+       (enq_op = enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]    \
+                       [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]       \
                        [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]          \
                        [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]    \
                        [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]    \
@@ -330,152 +331,218 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 {
        struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
        /* Single WS modes */
-       const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
+       const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
+       const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
+       const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
+       const event_dequeue_burst_t
+               sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
+       const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
+       const event_dequeue_burst_t
+               sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
+       const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
        const event_dequeue_burst_t
-               sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
+               sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t
+               sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
                        NIX_RX_FASTPATH_MODES
 #undef R
-               };
+       };
+
+       const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t
+               sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name,
+                       NIX_RX_FASTPATH_MODES
+#undef R
+       };
 
        /* Dual WS modes */
-       const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
+       const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_burst_t sso_hws_dual_deq_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
+       const event_dequeue_burst_t
+               sso_hws_dual_deq_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
-       const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
+       const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
        const event_dequeue_burst_t
-               sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
+               sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
                        NIX_RX_FASTPATH_MODES
 #undef R
-               };
+       };
 
-       const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
+       const event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
        const event_dequeue_burst_t
-               sso_hws_dual_deq_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
+               sso_hws_dual_deq_ca_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name,
+                       NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t
+               sso_hws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
                        NIX_RX_FASTPATH_MODES
 #undef R
                };
 
-       const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
+       const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
                NIX_RX_FASTPATH_MODES
 #undef R
        };
 
        const event_dequeue_burst_t
-               sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
+               sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] =                                         \
+                       cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
                        NIX_RX_FASTPATH_MODES
 #undef R
                };
 
+       const event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t
+               sso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
+       [f6][f5][f4][f3][f2][f1][f0] =                                         \
+                       cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
+                       NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
        /* Tx modes */
-       const event_tx_adapter_enqueue
-               sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
-#define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_##name,
+       const event_tx_adapter_enqueue_t
+               sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
+#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_##name,
                        NIX_TX_FASTPATH_MODES
 #undef T
                };
 
-       const event_tx_adapter_enqueue
-               sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
-#define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
+       const event_tx_adapter_enqueue_t
+               sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
+#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
                        NIX_TX_FASTPATH_MODES
 #undef T
                };
 
-       const event_tx_adapter_enqueue
-               sso_hws_dual_tx_adptr_enq[2][2][2][2][2][2] = {
-#define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
+       const event_tx_adapter_enqueue_t
+               sso_hws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
+#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
+       [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
                        NIX_TX_FASTPATH_MODES
 #undef T
                };
 
-       const event_tx_adapter_enqueue
-               sso_hws_dual_tx_adptr_enq_seg[2][2][2][2][2][2] = {
-#define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
-       [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
+       const event_tx_adapter_enqueue_t
+               sso_hws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
+#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
+       [f6][f5][f4][f3][f2][f1][f0] =                                         \
+                       cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
                        NIX_TX_FASTPATH_MODES
 #undef T
                };
@@ -494,6 +561,12 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                        CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
                                              sso_hws_deq_tmo_seg_burst);
                }
+               if (dev->is_ca_internal_port) {
+                       CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                             sso_hws_deq_ca_seg);
+                       CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
+                                             sso_hws_deq_ca_seg_burst);
+               }
        } else {
                CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
                CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
@@ -504,7 +577,14 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                        CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
                                              sso_hws_deq_tmo_burst);
                }
+               if (dev->is_ca_internal_port) {
+                       CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                             sso_hws_deq_ca);
+                       CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
+                                             sso_hws_deq_ca_burst);
+               }
        }
+       event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
 
        if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
                CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
@@ -519,6 +599,7 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
                event_dev->enqueue_forward_burst =
                        cn9k_sso_hws_dual_enq_fwd_burst;
+               event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
 
                if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
                        CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
@@ -532,6 +613,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                                        dev, event_dev->dequeue_burst,
                                        sso_hws_dual_deq_tmo_seg_burst);
                        }
+                       if (dev->is_ca_internal_port) {
+                               CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                                     sso_hws_dual_deq_ca_seg);
+                               CN9K_SET_EVDEV_DEQ_OP(
+                                       dev, event_dev->dequeue_burst,
+                                       sso_hws_dual_deq_ca_seg_burst);
+                       }
                } else {
                        CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
                                              sso_hws_dual_deq);
@@ -544,6 +632,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                                        dev, event_dev->dequeue_burst,
                                        sso_hws_dual_deq_tmo_burst);
                        }
+                       if (dev->is_ca_internal_port) {
+                               CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                                     sso_hws_dual_deq_ca);
+                               CN9K_SET_EVDEV_DEQ_OP(
+                                       dev, event_dev->dequeue_burst,
+                                       sso_hws_dual_deq_ca_burst);
+                       }
                }
 
                if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
@@ -930,7 +1025,8 @@ cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
        CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
        CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
 
-       *caps = 0;
+       *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
+               RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 
        return 0;
 }
@@ -964,7 +1060,7 @@ cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
        return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 }
 
-static struct rte_eventdev_ops cn9k_sso_dev_ops = {
+static struct eventdev_ops cn9k_sso_dev_ops = {
        .dev_infos_get = cn9k_sso_info_get,
        .dev_configure = cn9k_sso_dev_configure,
        .queue_def_conf = cnxk_sso_queue_def_conf,
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