event/cnxk: add option to configure getwork mode
[dpdk.git] / drivers / event / cnxk / cnxk_eventdev.c
index 3eab1ed..2a387ff 100644 (file)
@@ -28,12 +28,172 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
                                  RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;
 }
 
+int
+cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)
+{
+       char pool_name[RTE_MEMZONE_NAMESIZE];
+       uint32_t xaq_cnt, npa_aura_id;
+       const struct rte_memzone *mz;
+       struct npa_aura_s *aura;
+       static int reconfig_cnt;
+       int rc;
+
+       if (dev->xaq_pool) {
+               rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
+               if (rc < 0) {
+                       plt_err("Failed to release XAQ %d", rc);
+                       return rc;
+               }
+               rte_mempool_free(dev->xaq_pool);
+               dev->xaq_pool = NULL;
+       }
+
+       /*
+        * Allocate memory for Add work backpressure.
+        */
+       mz = rte_memzone_lookup(CNXK_SSO_FC_NAME);
+       if (mz == NULL)
+               mz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME,
+                                                sizeof(struct npa_aura_s) +
+                                                        RTE_CACHE_LINE_SIZE,
+                                                0, 0, RTE_CACHE_LINE_SIZE);
+       if (mz == NULL) {
+               plt_err("Failed to allocate mem for fcmem");
+               return -ENOMEM;
+       }
+
+       dev->fc_iova = mz->iova;
+       dev->fc_mem = mz->addr;
+
+       aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem +
+                                    RTE_CACHE_LINE_SIZE);
+       memset(aura, 0, sizeof(struct npa_aura_s));
+
+       aura->fc_ena = 1;
+       aura->fc_addr = dev->fc_iova;
+       aura->fc_hyst_bits = 0; /* Store count on all updates */
+
+       /* Taken from HRM 14.3.3(4) */
+       xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;
+       if (dev->xae_cnt)
+               xaq_cnt += dev->xae_cnt / dev->sso.xae_waes;
+       else
+               xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +
+                          (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);
+
+       plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
+       /* Setup XAQ based on number of nb queues. */
+       snprintf(pool_name, 30, "cnxk_xaq_buf_pool_%d", reconfig_cnt);
+       dev->xaq_pool = (void *)rte_mempool_create_empty(
+               pool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0,
+               rte_socket_id(), 0);
+
+       if (dev->xaq_pool == NULL) {
+               plt_err("Unable to create empty mempool.");
+               rte_memzone_free(mz);
+               return -ENOMEM;
+       }
+
+       rc = rte_mempool_set_ops_byname(dev->xaq_pool,
+                                       rte_mbuf_platform_mempool_ops(), aura);
+       if (rc != 0) {
+               plt_err("Unable to set xaqpool ops.");
+               goto alloc_fail;
+       }
+
+       rc = rte_mempool_populate_default(dev->xaq_pool);
+       if (rc < 0) {
+               plt_err("Unable to set populate xaqpool.");
+               goto alloc_fail;
+       }
+       reconfig_cnt++;
+       /* When SW does addwork (enqueue) check if there is space in XAQ by
+        * comparing fc_addr above against the xaq_lmt calculated below.
+        * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO
+        * to request XAQ to cache them even before enqueue is called.
+        */
+       dev->xaq_lmt =
+               xaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues);
+       dev->nb_xaq_cfg = xaq_cnt;
+
+       npa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id);
+       return roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id,
+                                      dev->nb_event_queues);
+alloc_fail:
+       rte_mempool_free(dev->xaq_pool);
+       rte_memzone_free(mz);
+       return rc;
+}
+
+int
+cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
+                      cnxk_sso_init_hws_mem_t init_hws_fn,
+                      cnxk_sso_hws_setup_t setup_hws_fn)
+{
+       struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+       int i;
+
+       for (i = 0; i < dev->nb_event_ports; i++) {
+               struct cnxk_sso_hws_cookie *ws_cookie;
+               void *ws;
+
+               /* Free memory prior to re-allocation if needed */
+               if (event_dev->data->ports[i] != NULL)
+                       ws = event_dev->data->ports[i];
+               else
+                       ws = init_hws_fn(dev, i);
+               if (ws == NULL)
+                       goto hws_fini;
+               ws_cookie = cnxk_sso_hws_get_cookie(ws);
+               ws_cookie->event_dev = event_dev;
+               ws_cookie->configured = 1;
+               event_dev->data->ports[i] = ws;
+               cnxk_sso_port_setup((struct rte_eventdev *)(uintptr_t)event_dev,
+                                   i, setup_hws_fn);
+       }
+
+       return 0;
+hws_fini:
+       for (i = i - 1; i >= 0; i--) {
+               event_dev->data->ports[i] = NULL;
+               rte_free(cnxk_sso_hws_get_cookie(event_dev->data->ports[i]));
+       }
+       return -ENOMEM;
+}
+
+void
+cnxk_sso_restore_links(const struct rte_eventdev *event_dev,
+                      cnxk_sso_link_t link_fn)
+{
+       struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+       uint16_t *links_map, hwgrp[CNXK_SSO_MAX_HWGRP];
+       int i, j;
+
+       for (i = 0; i < dev->nb_event_ports; i++) {
+               uint16_t nb_hwgrp = 0;
+
+               links_map = event_dev->data->links_map;
+               /* Point links_map to this port specific area */
+               links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);
+
+               for (j = 0; j < dev->nb_event_queues; j++) {
+                       if (links_map[j] == 0xdead)
+                               continue;
+                       hwgrp[nb_hwgrp] = j;
+                       nb_hwgrp++;
+               }
+
+               link_fn(dev, event_dev->data->ports[i], hwgrp, nb_hwgrp);
+       }
+}
+
 int
 cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)
 {
        struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
        struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
        uint32_t deq_tmo_ns;
+       int rc;
 
        deq_tmo_ns = conf->dequeue_timeout_ns;
 
@@ -67,6 +227,16 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)
                return -EINVAL;
        }
 
+       if (dev->xaq_pool) {
+               rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
+               if (rc < 0) {
+                       plt_err("Failed to release XAQ %d", rc);
+                       return rc;
+               }
+               rte_mempool_free(dev->xaq_pool);
+               dev->xaq_pool = NULL;
+       }
+
        dev->nb_event_queues = conf->nb_event_queues;
        dev->nb_event_ports = conf->nb_event_ports;
 
@@ -86,6 +256,25 @@ cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
        queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
 }
 
+int
+cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
+                    const struct rte_event_queue_conf *queue_conf)
+{
+       struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+
+       plt_sso_dbg("Queue=%d prio=%d", queue_id, queue_conf->priority);
+       /* Normalize <0-255> to <0-7> */
+       return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, 0xFF, 0xFF,
+                                         queue_conf->priority / 32);
+}
+
+void
+cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
+{
+       RTE_SET_USED(event_dev);
+       RTE_SET_USED(queue_id);
+}
+
 void
 cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
                       struct rte_event_port_conf *port_conf)
@@ -98,6 +287,145 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
        port_conf->enqueue_depth = 1;
 }
 
+int
+cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
+                   cnxk_sso_hws_setup_t hws_setup_fn)
+{
+       struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+       uintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0};
+       uint16_t q;
+
+       plt_sso_dbg("Port=%d", port_id);
+       if (event_dev->data->ports[port_id] == NULL) {
+               plt_err("Invalid port Id %d", port_id);
+               return -EINVAL;
+       }
+
+       for (q = 0; q < dev->nb_event_queues; q++) {
+               grps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q);
+               if (grps_base[q] == 0) {
+                       plt_err("Failed to get grp[%d] base addr", q);
+                       return -EINVAL;
+               }
+       }
+
+       hws_setup_fn(dev, event_dev->data->ports[port_id], grps_base);
+       plt_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
+       rte_mb();
+
+       return 0;
+}
+
+int
+cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
+                      uint64_t *tmo_ticks)
+{
+       RTE_SET_USED(event_dev);
+       *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
+
+       return 0;
+}
+
+static void
+parse_queue_param(char *value, void *opaque)
+{
+       struct cnxk_sso_qos queue_qos = {0};
+       uint8_t *val = (uint8_t *)&queue_qos;
+       struct cnxk_sso_evdev *dev = opaque;
+       char *tok = strtok(value, "-");
+       struct cnxk_sso_qos *old_ptr;
+
+       if (!strlen(value))
+               return;
+
+       while (tok != NULL) {
+               *val = atoi(tok);
+               tok = strtok(NULL, "-");
+               val++;
+       }
+
+       if (val != (&queue_qos.iaq_prcnt + 1)) {
+               plt_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
+               return;
+       }
+
+       dev->qos_queue_cnt++;
+       old_ptr = dev->qos_parse_data;
+       dev->qos_parse_data = rte_realloc(
+               dev->qos_parse_data,
+               sizeof(struct cnxk_sso_qos) * dev->qos_queue_cnt, 0);
+       if (dev->qos_parse_data == NULL) {
+               dev->qos_parse_data = old_ptr;
+               dev->qos_queue_cnt--;
+               return;
+       }
+       dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
+}
+
+static void
+parse_qos_list(const char *value, void *opaque)
+{
+       char *s = strdup(value);
+       char *start = NULL;
+       char *end = NULL;
+       char *f = s;
+
+       while (*s) {
+               if (*s == '[')
+                       start = s;
+               else if (*s == ']')
+                       end = s;
+
+               if (start && start < end) {
+                       *end = 0;
+                       parse_queue_param(start + 1, opaque);
+                       s = end;
+                       start = end;
+               }
+               s++;
+       }
+
+       free(f);
+}
+
+static int
+parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
+{
+       RTE_SET_USED(key);
+
+       /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
+        * isn't allowed. Everything is expressed in percentages, 0 represents
+        * default.
+        */
+       parse_qos_list(value, opaque);
+
+       return 0;
+}
+
+static void
+cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)
+{
+       struct rte_kvargs *kvlist;
+       uint8_t single_ws = 0;
+
+       if (devargs == NULL)
+               return;
+       kvlist = rte_kvargs_parse(devargs->args, NULL);
+       if (kvlist == NULL)
+               return;
+
+       rte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value,
+                          &dev->xae_cnt);
+       rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
+                          dev);
+       rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value,
+                          &single_ws);
+       rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value,
+                          &dev->gw_mode);
+       dev->dual_ws = !single_ws;
+       rte_kvargs_free(kvlist);
+}
+
 int
 cnxk_sso_init(struct rte_eventdev *event_dev)
 {
@@ -118,6 +446,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev)
        dev->sso.pci_dev = pci_dev;
 
        *(uint64_t *)mz->addr = (uint64_t)dev;
+       cnxk_sso_parse_devargs(dev, pci_dev->device.devargs);
 
        /* Initialize the base cnxk_dev object */
        rc = roc_sso_dev_init(&dev->sso);