cache_sz /= rte_lcore_count();
/* Create chunk pool. */
if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
- mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
+ mp_flags = RTE_MEMPOOL_F_SP_PUT | RTE_MEMPOOL_F_SC_GET;
plt_tim_dbg("Using single producer mode");
tim_ring->prod_type_sp = true;
}
return rc;
}
+static void
+cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)
+{
+ uint8_t prod_flag = !tim_ring->prod_type_sp;
+
+ /* [STATS] [DFB/FB] [SP][MP]*/
+ const rte_event_timer_arm_burst_t arm_burst[2][2][2] = {
+#define FP(_name, _f3, _f2, _f1, flags) \
+ [_f3][_f2][_f1] = cnxk_tim_arm_burst_##_name,
+ TIM_ARM_FASTPATH_MODES
+#undef FP
+ };
+
+ const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = {
+#define FP(_name, _f2, _f1, flags) \
+ [_f2][_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,
+ TIM_ARM_TMO_FASTPATH_MODES
+#undef FP
+ };
+
+ cnxk_tim_ops.arm_burst =
+ arm_burst[tim_ring->enable_stats][tim_ring->ena_dfb][prod_flag];
+ cnxk_tim_ops.arm_tmo_tick_burst =
+ arm_tmo_burst[tim_ring->enable_stats][tim_ring->ena_dfb];
+ cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst;
+}
+
+static void
+cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
+ struct rte_event_timer_adapter_info *adptr_info)
+{
+ struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
+
+ adptr_info->max_tmo_ns = tim_ring->max_tout;
+ adptr_info->min_resolution_ns = tim_ring->tck_nsec;
+ rte_memcpy(&adptr_info->conf, &adptr->data->conf,
+ sizeof(struct rte_event_timer_adapter_conf));
+}
+
static int
cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
{
struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
struct cnxk_tim_ring *tim_ring;
- int rc;
+ int i, rc;
if (dev == NULL)
return -ENODEV;
tim_ring->nb_timers = rcfg->nb_timers;
tim_ring->chunk_sz = dev->chunk_sz;
tim_ring->disable_npa = dev->disable_npa;
+ tim_ring->enable_stats = dev->enable_stats;
+
+ for (i = 0; i < dev->ring_ctl_cnt; i++) {
+ struct cnxk_tim_ctl *ring_ctl = &dev->ring_ctl_data[i];
+
+ if (ring_ctl->ring == tim_ring->ring_id) {
+ tim_ring->chunk_sz =
+ ring_ctl->chunk_slots ?
+ ((uint32_t)(ring_ctl->chunk_slots + 1) *
+ CNXK_TIM_CHUNK_ALIGNMENT) :
+ tim_ring->chunk_sz;
+ tim_ring->enable_stats = ring_ctl->enable_stats;
+ tim_ring->disable_npa = ring_ctl->disable_npa;
+ }
+ }
if (tim_ring->disable_npa) {
tim_ring->nb_chunks =
plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
+ /* Set fastpath ops. */
+ cnxk_tim_set_fp_ops(tim_ring);
+
/* Update SSO xae count. */
cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,
RTE_EVENT_TYPE_TIMER);
return 0;
}
+static void
+cnxk_tim_calibrate_start_tsc(struct cnxk_tim_ring *tim_ring)
+{
+#define CNXK_TIM_CALIB_ITER 1E6
+ uint32_t real_bkt, bucket;
+ int icount, ecount = 0;
+ uint64_t bkt_cyc;
+
+ for (icount = 0; icount < CNXK_TIM_CALIB_ITER; icount++) {
+ real_bkt = plt_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;
+ bkt_cyc = cnxk_tim_cntvct();
+ bucket = (bkt_cyc - tim_ring->ring_start_cyc) /
+ tim_ring->tck_int;
+ bucket = bucket % (tim_ring->nb_bkts);
+ tim_ring->ring_start_cyc =
+ bkt_cyc - (real_bkt * tim_ring->tck_int);
+ if (bucket != real_bkt)
+ ecount++;
+ }
+ tim_ring->last_updt_cyc = bkt_cyc;
+ plt_tim_dbg("Bucket mispredict %3.2f distance %d\n",
+ 100 - (((double)(icount - ecount) / (double)icount) * 100),
+ bucket - real_bkt);
+}
+
+static int
+cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr)
+{
+ struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
+ struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
+ int rc;
+
+ if (dev == NULL)
+ return -ENODEV;
+
+ rc = roc_tim_lf_enable(&dev->tim, tim_ring->ring_id,
+ &tim_ring->ring_start_cyc, NULL);
+ if (rc < 0)
+ return rc;
+
+ tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq());
+ tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts;
+ tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int);
+ tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts);
+
+ cnxk_tim_calibrate_start_tsc(tim_ring);
+
+ return rc;
+}
+
+static int
+cnxk_tim_ring_stop(const struct rte_event_timer_adapter *adptr)
+{
+ struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
+ struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
+ int rc;
+
+ if (dev == NULL)
+ return -ENODEV;
+
+ rc = roc_tim_lf_disable(&dev->tim, tim_ring->ring_id);
+ if (rc < 0)
+ plt_err("Failed to disable timer ring");
+
+ return rc;
+}
+
+static int
+cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter,
+ struct rte_event_timer_adapter_stats *stats)
+{
+ struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv;
+ uint64_t bkt_cyc = cnxk_tim_cntvct() - tim_ring->ring_start_cyc;
+
+ stats->evtim_exp_count =
+ __atomic_load_n(&tim_ring->arm_cnt, __ATOMIC_RELAXED);
+ stats->ev_enq_count = stats->evtim_exp_count;
+ stats->adapter_tick_count =
+ rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div);
+ return 0;
+}
+
+static int
+cnxk_tim_stats_reset(const struct rte_event_timer_adapter *adapter)
+{
+ struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv;
+
+ __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED);
+ return 0;
+}
+
int
cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
uint32_t *caps,
struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
RTE_SET_USED(flags);
- RTE_SET_USED(ops);
if (dev == NULL)
return -ENODEV;
cnxk_tim_ops.init = cnxk_tim_ring_create;
cnxk_tim_ops.uninit = cnxk_tim_ring_free;
+ cnxk_tim_ops.start = cnxk_tim_ring_start;
+ cnxk_tim_ops.stop = cnxk_tim_ring_stop;
+ cnxk_tim_ops.get_info = cnxk_tim_ring_info_get;
+
+ if (dev->enable_stats) {
+ cnxk_tim_ops.stats_get = cnxk_tim_stats_get;
+ cnxk_tim_ops.stats_reset = cnxk_tim_stats_reset;
+ }
/* Store evdev pointer for later use. */
dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
+ *ops = &cnxk_tim_ops;
+
+ return 0;
+}
+
+static void
+cnxk_tim_parse_ring_param(char *value, void *opaque)
+{
+ struct cnxk_tim_evdev *dev = opaque;
+ struct cnxk_tim_ctl ring_ctl = {0};
+ char *tok = strtok(value, "-");
+ struct cnxk_tim_ctl *old_ptr;
+ uint16_t *val;
+
+ val = (uint16_t *)&ring_ctl;
+
+ if (!strlen(value))
+ return;
+
+ while (tok != NULL) {
+ *val = atoi(tok);
+ tok = strtok(NULL, "-");
+ val++;
+ }
+
+ if (val != (&ring_ctl.enable_stats + 1)) {
+ plt_err("Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]");
+ return;
+ }
+
+ dev->ring_ctl_cnt++;
+ old_ptr = dev->ring_ctl_data;
+ dev->ring_ctl_data =
+ rte_realloc(dev->ring_ctl_data,
+ sizeof(struct cnxk_tim_ctl) * dev->ring_ctl_cnt, 0);
+ if (dev->ring_ctl_data == NULL) {
+ dev->ring_ctl_data = old_ptr;
+ dev->ring_ctl_cnt--;
+ return;
+ }
+
+ dev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl;
+}
+
+static void
+cnxk_tim_parse_ring_ctl_list(const char *value, void *opaque)
+{
+ char *s = strdup(value);
+ char *start = NULL;
+ char *end = NULL;
+ char *f = s;
+
+ while (*s) {
+ if (*s == '[')
+ start = s;
+ else if (*s == ']')
+ end = s;
+
+ if (start && start < end) {
+ *end = 0;
+ cnxk_tim_parse_ring_param(start + 1, opaque);
+ start = end;
+ s = end;
+ }
+ s++;
+ }
+
+ free(f);
+}
+
+static int
+cnxk_tim_parse_kvargs_dict(const char *key, const char *value, void *opaque)
+{
+ RTE_SET_USED(key);
+
+ /* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ','
+ * isn't allowed. 0 represents default.
+ */
+ cnxk_tim_parse_ring_ctl_list(value, opaque);
return 0;
}
rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
&dev->disable_npa);
+ rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
+ &dev->chunk_slots);
+ rte_kvargs_process(kvlist, CNXK_TIM_STATS_ENA, &parse_kvargs_flag,
+ &dev->enable_stats);
+ rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
+ &dev->min_ring_cnt);
+ rte_kvargs_process(kvlist, CNXK_TIM_RING_CTL,
+ &cnxk_tim_parse_kvargs_dict, &dev);
rte_kvargs_free(kvlist);
}
cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
dev->tim.roc_sso = sso;
+ dev->tim.nb_lfs = dev->min_ring_cnt;
rc = roc_tim_init(&dev->tim);
if (rc < 0) {
plt_err("Failed to initialize roc tim resources");
return;
}
dev->nb_rings = rc;
- dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
+
+ if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
+ dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
+ dev->chunk_sz =
+ (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
+ } else {
+ dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
+ }
}
void
git.droids-corp.org / dpdk.git / blobdiff