event/cnxk: add timer arm routine

[dpdk.git] / drivers / event / cnxk / cnxk_tim_evdev.c

diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c
index d93b37e..ecc952a 100644 (file)
--- a/drivers/event/cnxk/cnxk_tim_evdev.c
+++ b/drivers/event/cnxk/cnxk_tim_evdev.c
@@ -76,6 +76,33 @@ free:
        return rc;
 }
 
+static void
+cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)
+{
+       uint8_t prod_flag = !tim_ring->prod_type_sp;
+
+       /* [DFB/FB] [SP][MP]*/
+       const rte_event_timer_arm_burst_t arm_burst[2][2] = {
+#define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name,
+               TIM_ARM_FASTPATH_MODES
+#undef FP
+       };
+
+       cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag];
+}
+
+static void
+cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
+                      struct rte_event_timer_adapter_info *adptr_info)
+{
+       struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
+
+       adptr_info->max_tmo_ns = tim_ring->max_tout;
+       adptr_info->min_resolution_ns = tim_ring->tck_nsec;
+       rte_memcpy(&adptr_info->conf, &adptr->data->conf,
+                  sizeof(struct rte_event_timer_adapter_conf));
+}
+
 static int
 cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
 {
@@ -161,6 +188,14 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
        plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
        plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
 
+       /* Set fastpath ops. */
+       cnxk_tim_set_fp_ops(tim_ring);
+
+       /* Update SSO xae count. */
+       cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,
+                             RTE_EVENT_TYPE_TIMER);
+       cnxk_sso_xae_reconfigure(dev->event_dev);
+
        plt_tim_dbg(
                "Total memory used %" PRIu64 "MB\n",
                (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +
@@ -213,6 +248,7 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 
        cnxk_tim_ops.init = cnxk_tim_ring_create;
        cnxk_tim_ops.uninit = cnxk_tim_ring_free;
+       cnxk_tim_ops.get_info = cnxk_tim_ring_info_get;
 
        /* Store evdev pointer for later use. */
        dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
@@ -235,6 +271,10 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)
 
        rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
                           &dev->disable_npa);
+       rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
+                          &dev->chunk_slots);
+       rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
+                          &dev->min_ring_cnt);
 
        rte_kvargs_free(kvlist);
 }
@@ -260,6 +300,7 @@ cnxk_tim_init(struct roc_sso *sso)
        cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
 
        dev->tim.roc_sso = sso;
+       dev->tim.nb_lfs = dev->min_ring_cnt;
        rc = roc_tim_init(&dev->tim);
        if (rc < 0) {
                plt_err("Failed to initialize roc tim resources");
@@ -267,7 +308,14 @@ cnxk_tim_init(struct roc_sso *sso)
                return;
        }
        dev->nb_rings = rc;
-       dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
+
+       if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
+           dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
+               dev->chunk_sz =
+                       (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
+       } else {
+               dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
+       }
 }
 
 void