net/ena: fix meta descriptor DF flag setup

[dpdk.git] / drivers / event / cnxk / cnxk_tim_evdev.h

diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h
index c369f6f..91a90ee 100644 (file)
--- a/drivers/event/cnxk/cnxk_tim_evdev.h
+++ b/drivers/event/cnxk/cnxk_tim_evdev.h
@@ -31,6 +31,7 @@
 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
 #define CNXK_TIM_MIN_CHUNK_SLOTS    (0x1)
 #define CNXK_TIM_MAX_CHUNK_SLOTS    (0x1FFE)
+#define CNXK_TIM_MAX_POOL_CACHE_SZ  (128)
 
 #define CN9K_TIM_MIN_TMO_TKS (256)
 
@@ -39,6 +40,7 @@
 #define CNXK_TIM_STATS_ENA   "tim_stats_ena"
 #define CNXK_TIM_RINGS_LMT   "tim_rings_lmt"
 #define CNXK_TIM_RING_CTL    "tim_ring_ctl"
+#define CNXK_TIM_EXT_CLK     "tim_eclk_freq"
 
 #define CNXK_TIM_SP       0x1
 #define CNXK_TIM_MP       0x2
@@ -90,20 +92,14 @@ struct cnxk_tim_evdev {
        uint32_t chunk_sz;
        /* Dev args */
        uint8_t disable_npa;
-       uint16_t chunk_slots;
-       uint16_t min_ring_cnt;
+       uint32_t chunk_slots;
+       uint32_t min_ring_cnt;
        uint8_t enable_stats;
        uint16_t ring_ctl_cnt;
+       uint64_t ext_clk_freq[ROC_TIM_CLK_SRC_INVALID];
        struct cnxk_tim_ctl *ring_ctl_data;
 };
 
-enum cnxk_tim_clk_src {
-       CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
-       CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
-       CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
-       CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
-};
-
 struct cnxk_tim_bkt {
        uint64_t first_chunk;
        union {
@@ -139,6 +135,7 @@ struct cnxk_tim_ring {
        uint8_t enable_stats;
        uint8_t disable_npa;
        uint8_t ena_dfb;
+       uint8_t ena_periodic;
        uint16_t ring_id;
        uint32_t aura;
        uint64_t nb_timers;
@@ -146,7 +143,7 @@ struct cnxk_tim_ring {
        uint64_t max_tout;
        uint64_t nb_chunks;
        uint64_t chunk_sz;
-       enum cnxk_tim_clk_src clk_src;
+       enum roc_tim_clk_src clk_src;
 } __rte_cache_aligned;
 
 struct cnxk_tim_ent {
@@ -166,31 +163,10 @@ cnxk_tim_priv_get(void)
        return mz->addr;
 }
 
-static inline uint64_t
-cnxk_tim_min_tmo_ticks(uint64_t freq)
-{
-       if (roc_model_runtime_is_cn9k())
-               return CN9K_TIM_MIN_TMO_TKS;
-       else /* CN10K min tick is of 1us */
-               return freq / USECPERSEC;
-}
-
-static inline uint64_t
-cnxk_tim_min_resolution_ns(uint64_t freq)
-{
-       return NSECPERSEC / freq;
-}
-
-static inline enum roc_tim_clk_src
-cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
+static inline long double
+cnxk_tim_ns_per_tck(uint64_t freq)
 {
-       switch (clk_src) {
-       case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
-               return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
-                                                          ROC_TIM_CLK_SRC_GTI;
-       default:
-               return ROC_TIM_CLK_SRC_INVALID;
-       }
+       return (long double)NSECPERSEC / freq;
 }
 
 #ifdef RTE_ARCH_ARM64
@@ -225,6 +201,53 @@ cnxk_tim_cntfrq(void)
 }
 #endif
 
+static inline enum roc_tim_clk_src
+cnxk_tim_convert_clk_src(enum rte_event_timer_adapter_clk_src clk_src)
+{
+       switch (clk_src) {
+       case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
+               return ROC_TIM_CLK_SRC_GTI;
+       case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0:
+               return ROC_TIM_CLK_SRC_10NS;
+       case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1:
+               return ROC_TIM_CLK_SRC_GPIO;
+       case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2:
+               return ROC_TIM_CLK_SRC_PTP;
+       case RTE_EVENT_TIMER_ADAPTER_EXT_CLK3:
+               return roc_model_constant_is_cn9k() ? ROC_TIM_CLK_SRC_INVALID :
+                                                     ROC_TIM_CLK_SRC_SYNCE;
+       default:
+               return ROC_TIM_CLK_SRC_INVALID;
+       }
+}
+
+static inline int
+cnxk_tim_get_clk_freq(struct cnxk_tim_evdev *dev, enum roc_tim_clk_src clk_src,
+                     uint64_t *freq)
+{
+       if (freq == NULL)
+               return -EINVAL;
+
+       PLT_SET_USED(dev);
+       switch (clk_src) {
+       case ROC_TIM_CLK_SRC_GTI:
+               *freq = cnxk_tim_cntfrq();
+               break;
+       case ROC_TIM_CLK_SRC_10NS:
+               *freq = 1E8;
+               break;
+       case ROC_TIM_CLK_SRC_GPIO:
+       case ROC_TIM_CLK_SRC_PTP:
+       case ROC_TIM_CLK_SRC_SYNCE:
+               *freq = dev->ext_clk_freq[clk_src];
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
 #define TIM_ARM_FASTPATH_MODES                                                 \
        FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP)                        \
        FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP)                        \
@@ -267,7 +290,7 @@ cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,
 
 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
                      uint32_t *caps,
-                     const struct rte_event_timer_adapter_ops **ops);
+                     const struct event_timer_adapter_ops **ops);
 
 void cnxk_tim_init(struct roc_sso *sso);
 void cnxk_tim_fini(void);