#include <rte_string_fns.h>
#include <rte_eventdev.h>
-#include <rte_eventdev_pmd.h>
+#include <eventdev_pmd.h>
#include "dlb_priv.h"
#include "dlb_iface.h"
/* The credit window is one high water mark of QEs */
qm_port->dir_pushcount_at_credit_expiry = 0;
qm_port->cached_dir_credits = cfg.dir_credit_high_watermark;
- qm_port->cq_depth = cfg.cq_depth;
/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
* the effective depth is smaller.
*/
{
struct dlb_hw_dev *handle = &dlb->qm_instance;
struct dlb_create_dir_queue_args cfg;
- struct dlb_cmd_response response;
+ struct dlb_cmd_response response = {0};
int32_t ret;
cfg.response = (uintptr_t)&response;
/* Interrupts not supported by PF PMD */
return 1;
} else if (dlb->umwait_allowed) {
+ struct rte_power_monitor_cond pmc;
volatile struct dlb_dequeue_qe *cq_base;
union {
uint64_t raw_qe[2];
else
expected_value = 0;
- rte_power_monitor(monitor_addr, expected_value,
- qe_mask.raw_qe[1], timeout + start_ticks,
- sizeof(uint64_t));
+ pmc.addr = monitor_addr;
+ pmc.val = expected_value;
+ pmc.mask = qe_mask.raw_qe[1];
+ pmc.size = sizeof(uint64_t);
+
+ rte_power_monitor(&pmc, timeout + start_ticks);
DLB_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);
} else {
{
struct dlb_hw_dev *handle = &dlb->qm_instance;
struct dlb_get_ldb_queue_depth_args cfg;
- struct dlb_cmd_response response;
+ struct dlb_cmd_response response = {0};
int ret;
cfg.queue_id = queue->qm_queue.id;
{
struct dlb_hw_dev *handle = &dlb->qm_instance;
struct dlb_get_dir_queue_depth_args cfg;
- struct dlb_cmd_response response;
+ struct dlb_cmd_response response = {0};
int ret;
cfg.queue_id = queue->qm_queue.id;