#include <rte_malloc.h>
#include <rte_errno.h>
-#include "base/dlb2_resource.h"
+#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */
+
+#include "base/dlb2_regs_new.h"
+#include "base/dlb2_hw_types_new.h"
+#include "base/dlb2_resource_new.h"
#include "base/dlb2_osdep.h"
-#include "base/dlb2_regs.h"
#include "dlb2_main.h"
#include "../dlb2_user.h"
#include "../dlb2_priv.h"
#define NO_OWNER_VF 0 /* PF ONLY! */
#define NOT_VF_REQ false /* PF ONLY! */
-#define DLB2_PCI_CFG_SPACE_SIZE 256
#define DLB2_PCI_CAP_POINTER 0x34
#define DLB2_PCI_CAP_NEXT(hdr) (((hdr) >> 8) & 0xFC)
#define DLB2_PCI_CAP_ID(hdr) ((hdr) & 0xFF)
-#define DLB2_PCI_EXT_CAP_NEXT(hdr) (((hdr) >> 20) & 0xFFC)
-#define DLB2_PCI_EXT_CAP_ID(hdr) ((hdr) & 0xFFFF)
-#define DLB2_PCI_EXT_CAP_ID_ERR 1
-#define DLB2_PCI_ERR_UNCOR_MASK 8
-#define DLB2_PCI_ERR_UNC_UNSUP 0x00100000
-#define DLB2_PCI_EXP_DEVCTL 8
#define DLB2_PCI_LNKCTL 16
#define DLB2_PCI_SLTCTL 24
#define DLB2_PCI_RTCTL 28
#define DLB2_PCI_LNKCTL2 48
#define DLB2_PCI_SLTCTL2 56
#define DLB2_PCI_CMD 4
-#define DLB2_PCI_X_CMD 2
#define DLB2_PCI_EXP_DEVSTA 10
#define DLB2_PCI_EXP_DEVSTA_TRPND 0x20
#define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000
#define DLB2_PCI_CAP_ID_EXP 0x10
#define DLB2_PCI_CAP_ID_MSIX 0x11
-#define DLB2_PCI_EXT_CAP_ID_PAS 0x1B
#define DLB2_PCI_EXT_CAP_ID_PRI 0x13
#define DLB2_PCI_EXT_CAP_ID_ACS 0xD
#define DLB2_PCI_ACS_UF 0x10
#define DLB2_PCI_ACS_EC 0x20
-static int
-dlb2_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id)
-{
- uint32_t hdr;
- size_t sz;
- int pos;
-
- pos = DLB2_PCI_CFG_SPACE_SIZE;
- sz = sizeof(hdr);
-
- while (pos > 0xFF) {
- if (rte_pci_read_config(pdev, &hdr, sz, pos) != (int)sz)
- return -1;
-
- if (DLB2_PCI_EXT_CAP_ID(hdr) == id)
- return pos;
-
- pos = DLB2_PCI_EXT_CAP_NEXT(hdr);
- }
-
- return -1;
-}
-
static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)
{
uint8_t pos;
static void dlb2_pf_enable_pm(struct dlb2_dev *dlb2_dev)
{
- dlb2_clr_pmcsr_disable(&dlb2_dev->hw);
+ int version;
+ version = DLB2_HW_DEVICE_FROM_PCI_ID(dlb2_dev->pdev);
+
+ dlb2_clr_pmcsr_disable(&dlb2_dev->hw, version);
}
#define DLB2_READY_RETRY_LIMIT 1000
-static int dlb2_pf_wait_for_device_ready(struct dlb2_dev *dlb2_dev)
+static int dlb2_pf_wait_for_device_ready(struct dlb2_dev *dlb2_dev,
+ int dlb_version)
{
u32 retries = 0;
/* Allow at least 1s for the device to become active after power-on */
for (retries = 0; retries < DLB2_READY_RETRY_LIMIT; retries++) {
- union dlb2_cfg_mstr_cfg_diagnostic_idle_status idle;
- union dlb2_cfg_mstr_cfg_pm_status pm_st;
+ u32 idle_val;
+ u32 idle_dlb_func_idle;
+ u32 pm_st_val;
+ u32 pm_st_pmsm;
u32 addr;
- addr = DLB2_CFG_MSTR_CFG_PM_STATUS;
- pm_st.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);
- addr = DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS;
- idle.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);
- if (pm_st.field.pmsm == 1 && idle.field.dlb_func_idle == 1)
+ addr = DLB2_CM_CFG_PM_STATUS(dlb_version);
+ pm_st_val = DLB2_CSR_RD(&dlb2_dev->hw, addr);
+ addr = DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS(dlb_version);
+ idle_val = DLB2_CSR_RD(&dlb2_dev->hw, addr);
+ idle_dlb_func_idle = idle_val &
+ DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DLB_FUNC_IDLE;
+ pm_st_pmsm = pm_st_val & DLB2_CM_CFG_PM_STATUS_PMSM;
+ if (pm_st_pmsm && idle_dlb_func_idle)
break;
rte_delay_ms(1);
{
struct dlb2_dev *dlb2_dev;
int ret = 0;
+ int dlb_version = 0;
DLB2_INFO(dlb2_dev, "probe\n");
goto dlb2_dev_malloc_fail;
}
+ dlb_version = DLB2_HW_DEVICE_FROM_PCI_ID(pdev);
+
/* PCI Bus driver has already mapped bar space into process.
* Save off our IO register and FUNC addresses.
*/
*/
dlb2_pf_enable_pm(dlb2_dev);
- ret = dlb2_pf_wait_for_device_ready(dlb2_dev);
+ ret = dlb2_pf_wait_for_device_ready(dlb2_dev, dlb_version);
if (ret)
goto wait_for_device_ready_fail;
if (ret)
goto init_driver_state_fail;
- ret = dlb2_resource_init(&dlb2_dev->hw);
+ ret = dlb2_resource_init(&dlb2_dev->hw, dlb_version);
if (ret)
goto resource_init_fail;
return pcie_cap_offset;
}
- off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;
+ off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL;
if (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2)
dev_ctl_word = 0;
slt_word2 = 0;
off = DLB2_PCI_EXT_CAP_ID_PRI;
- pri_cap_offset = dlb2_pci_find_ext_capability(pdev, off);
+ pri_cap_offset = rte_pci_find_ext_capability(pdev, off);
if (pri_cap_offset >= 0) {
off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;
return -1;
}
- off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;
+ off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL;
ret = rte_pci_read_config(pdev, &devctl_word, 2, off);
if (ret != 2) {
DLB2_LOG_ERR("[%s()] failed to read the pcie device control\n",
/* Restore PCI config state */
if (pcie_cap_offset >= 0) {
- off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;
+ off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL;
ret = rte_pci_write_config(pdev, &dev_ctl_word, 2, off);
if (ret != 2) {
DLB2_LOG_ERR("[%s()] failed to write the pcie device control at offset %d\n",
}
}
- off = DLB2_PCI_EXT_CAP_ID_ERR;
- err_cap_offset = dlb2_pci_find_ext_capability(pdev, off);
+ off = RTE_PCI_EXT_CAP_ID_ERR;
+ err_cap_offset = rte_pci_find_ext_capability(pdev, off);
if (err_cap_offset >= 0) {
uint32_t tmp;
}
off = DLB2_PCI_EXT_CAP_ID_ACS;
- acs_cap_offset = dlb2_pci_find_ext_capability(pdev, off);
+ acs_cap_offset = rte_pci_find_ext_capability(pdev, off);
if (acs_cap_offset >= 0) {
uint16_t acs_cap, acs_ctrl, acs_mask;
NOT_VF_REQ,
PF_ID_ZERO);
}
+
+int
+dlb2_pf_create_dir_queue(struct dlb2_hw *hw,
+ u32 id,
+ struct dlb2_create_dir_queue_args *args,
+ struct dlb2_cmd_response *resp)
+{
+ return dlb2_hw_create_dir_queue(hw, id, args, resp, NOT_VF_REQ,
+ PF_ID_ZERO);
+}
+
+int
+dlb2_pf_start_domain(struct dlb2_hw *hw,
+ u32 id,
+ struct dlb2_start_domain_args *args,
+ struct dlb2_cmd_response *resp)
+{
+ return dlb2_hw_start_domain(hw, id, args, resp, NOT_VF_REQ,
+ PF_ID_ZERO);
+}
git.droids-corp.org / dpdk.git / blobdiff