#include <rte_memory.h>
#include <rte_pci.h>
#include <rte_bus_vdev.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include <rte_cryptodev.h>
#include <rte_event_eth_rx_adapter.h>
#include <rte_event_eth_tx_adapter.h>
* Soft Event Flow is DPCI Instance
*/
-/* Dynamic logging identified for mempool */
-int dpaa2_logtype_event;
#define DPAA2_EV_TX_RETRY_COUNT 10000
static uint16_t
/* Affine current thread context to a qman portal */
ret = dpaa2_affine_qbman_swp();
if (ret < 0) {
- DPAA2_EVENTDEV_ERR("Failure in affining portal");
+ DPAA2_EVENTDEV_ERR(
+ "Failed to allocate IO portal, tid: %d\n",
+ rte_gettid());
return 0;
}
}
qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
if (event->sched_type == RTE_SCHED_TYPE_ATOMIC
- && event->mbuf->seqn) {
- uint8_t dqrr_index = event->mbuf->seqn - 1;
+ && *dpaa2_seqn(event->mbuf)) {
+ uint8_t dqrr_index =
+ *dpaa2_seqn(event->mbuf) - 1;
qbman_eq_desc_set_dca(&eqdesc[loop], 1,
dqrr_index, 0);
rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
rte_free(ev_temp);
- ev->mbuf->seqn = dqrr_index + 1;
+ *dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
DPAA2_PER_LCORE_DQRR_SIZE++;
DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
/* Affine current thread context to a qman portal */
ret = dpaa2_affine_qbman_swp();
if (ret < 0) {
- DPAA2_EVENTDEV_ERR("Failure in affining portal");
+ DPAA2_EVENTDEV_ERR(
+ "Failed to allocate IO portal, tid: %d\n",
+ rte_gettid());
return 0;
}
}
if (DPAA2_PER_LCORE_DQRR_HELD & (1 << i)) {
qbman_swp_dqrr_idx_consume(swp, i);
DPAA2_PER_LCORE_DQRR_SIZE--;
- DPAA2_PER_LCORE_DQRR_MBUF(i)->seqn =
+ *dpaa2_seqn(DPAA2_PER_LCORE_DQRR_MBUF(i)) =
DPAA2_INVALID_MBUF_SEQN;
}
i++;
dev_info->max_event_priority_levels =
DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
dev_info->max_event_ports = rte_fslmc_get_device_count(DPAA2_IO);
- /* we only support dpio upto number of cores*/
+ /* we only support dpio up to number of cores */
if (dev_info->max_event_ports > rte_lcore_count())
dev_info->max_event_ports = rte_lcore_count();
dev_info->max_event_port_dequeue_depth =
RTE_EVENT_DEV_CAP_BURST_MODE|
RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
- RTE_EVENT_DEV_CAP_NONSEQ_MODE;
+ RTE_EVENT_DEV_CAP_NONSEQ_MODE |
+ RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
+ RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;
}
DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
port_conf->enqueue_depth =
DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
- port_conf->disable_implicit_release = 0;
+ port_conf->event_port_cfg = 0;
}
static int
EVENTDEV_INIT_FUNC_TRACE();
+ if (portal == NULL)
+ return;
+
/* TODO: Cleanup is required when ports are in linked state. */
if (portal->is_port_linked)
DPAA2_EVENTDEV_WARN("Event port must be unlinked before release");
- if (portal)
- rte_free(portal);
-
- portal = NULL;
+ rte_free(portal);
}
static int
};
RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);
-
-RTE_INIT(dpaa2_eventdev_init_log)
-{
- dpaa2_logtype_event = rte_log_register("pmd.event.dpaa2");
- if (dpaa2_logtype_event >= 0)
- rte_log_set_level(dpaa2_logtype_event, RTE_LOG_NOTICE);
-}
+RTE_LOG_REGISTER(dpaa2_logtype_event, pmd.event.dpaa2, NOTICE);