net/igc: fix build with gcc optimization level 0

[dpdk.git] / drivers / event / octeontx / ssovf_evdev.h

diff --git a/drivers/event/octeontx/ssovf_evdev.h b/drivers/event/octeontx/ssovf_evdev.h
index 1f5066c..1016315 100644 (file)
--- a/drivers/event/octeontx/ssovf_evdev.h
+++ b/drivers/event/octeontx/ssovf_evdev.h
@@ -86,8 +86,6 @@
 #define SSO_GRP_GET_PRIORITY              0x7
 #define SSO_GRP_SET_PRIORITY              0x8
 
-#define SSOVF_SELFTEST_ARG               ("selftest")
-
 /*
  * In Cavium OCTEON TX SoC, all accesses to the device registers are
  * implictly strongly ordered. So, The relaxed version of IO operation is
@@ -146,6 +144,12 @@ struct ssovf_evdev {
        uint32_t min_deq_timeout_ns;
        uint32_t max_deq_timeout_ns;
        int32_t max_num_events;
+       uint32_t available_events;
+       uint16_t rxq_pools;
+       uint64_t *rxq_pool_array;
+       uint8_t *rxq_pool_rcnt;
+       uint16_t tim_ring_cnt;
+       uint16_t *tim_ring_ids;
 } __rte_cache_aligned;
 
 /* Event port aka HWS */
@@ -157,6 +161,7 @@ struct ssows {
        uint8_t *getwork;
        uint8_t *grps[SSO_MAX_VHGRP];
        uint8_t port;
+       void *lookup_mem;
 } __rte_cache_aligned;
 
 static inline struct ssovf_evdev *
@@ -182,5 +187,6 @@ int ssovf_info(struct ssovf_info *info);
 void *ssovf_bar(enum ssovf_type, uint8_t id, uint8_t bar);
 int test_eventdev_octeontx(void);
 void ssovf_fastpath_fns_set(struct rte_eventdev *dev);
+void *octeontx_fastpath_lookup_mem_get(void);
 
 #endif /* __SSOVF_EVDEV_H__ */