dpaa2: prepare for 32-bit build

[dpdk.git] / drivers / event / octeontx / ssovf_evdev.h

diff --git a/drivers/event/octeontx/ssovf_evdev.h b/drivers/event/octeontx/ssovf_evdev.h
index 8fe18f5..d1825b4 100644 (file)
--- a/drivers/event/octeontx/ssovf_evdev.h
+++ b/drivers/event/octeontx/ssovf_evdev.h
@@ -22,6 +22,7 @@
 #define ssovf_log_dbg(fmt, ...) SSOVF_LOG(DEBUG, fmt, ##__VA_ARGS__)
 #define ssovf_log_err(fmt, ...) SSOVF_LOG(ERR, fmt, ##__VA_ARGS__)
 #define ssovf_func_trace ssovf_log_dbg
+#define ssovf_log_selftest ssovf_log_info
 
 #define SSO_MAX_VHGRP                     (64)
 #define SSO_MAX_VHWS                      (32)
@@ -79,6 +80,8 @@
 #define SSO_GRP_GET_PRIORITY              0x7
 #define SSO_GRP_SET_PRIORITY              0x8
 
+#define SSOVF_SELFTEST_ARG               ("selftest")
+
 /*
  * In Cavium OcteonTX SoC, all accesses to the device registers are
  * implictly strongly ordered. So, The relaxed version of IO operation is
@@ -163,5 +166,6 @@ uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[],
                uint16_t nb_events, uint64_t timeout_ticks);
 void ssows_flush_events(struct ssows *ws, uint8_t queue_id);
 void ssows_reset(struct ssows *ws);
+int test_eventdev_octeontx(void);
 
 #endif /* __SSOVF_EVDEV_H__ */