event/octeontx2: fix build for O1 optimization

[dpdk.git] / drivers / event / octeontx / timvf_evdev.h

diff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h
index 7663dc3..d0e5921 100644 (file)
--- a/drivers/event/octeontx/timvf_evdev.h
+++ b/drivers/event/octeontx/timvf_evdev.h
@@ -1,5 +1,4 @@
-/*
- * SPDX-License-Identifier: BSD-3-Clause
+/* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2017 Cavium, Inc
  */
 
@@ -25,6 +24,7 @@
 #include <rte_reciprocal.h>
 
 #include <octeontx_mbox.h>
+#include <octeontx_fpavf.h>
 
 #define timvf_log(level, fmt, args...) \
        rte_log(RTE_LOG_ ## level, otx_logtype_timvf, \
@@ -75,6 +75,33 @@
 #define TIM_VRING_AURA                         (0x108)
 #define TIM_VRING_REL                          (0x110)
 
+#define TIM_CTL1_W0_S_BUCKET                   20
+#define TIM_CTL1_W0_M_BUCKET                   ((1ull << (40 - 20)) - 1)
+
+#define TIM_BUCKET_W1_S_NUM_ENTRIES            (0) /*Shift*/
+#define TIM_BUCKET_W1_M_NUM_ENTRIES            ((1ull << (32 - 0)) - 1)
+#define TIM_BUCKET_W1_S_SBT                    (32)
+#define TIM_BUCKET_W1_M_SBT                    ((1ull << (33 - 32)) - 1)
+#define TIM_BUCKET_W1_S_HBT                    (33)
+#define TIM_BUCKET_W1_M_HBT                    ((1ull << (34 - 33)) - 1)
+#define TIM_BUCKET_W1_S_BSK                    (34)
+#define TIM_BUCKET_W1_M_BSK                    ((1ull << (35 - 34)) - 1)
+#define TIM_BUCKET_W1_S_LOCK                   (40)
+#define TIM_BUCKET_W1_M_LOCK                   ((1ull << (48 - 40)) - 1)
+#define TIM_BUCKET_W1_S_CHUNK_REMAINDER                (48)
+#define TIM_BUCKET_W1_M_CHUNK_REMAINDER                ((1ull << (64 - 48)) - 1)
+
+#define TIM_BUCKET_SEMA        \
+       (TIM_BUCKET_CHUNK_REMAIN)
+
+#define TIM_BUCKET_CHUNK_REMAIN \
+       (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
+
+#define TIM_BUCKET_LOCK \
+       (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
+
+#define TIM_BUCKET_SEMA_WLOCK \
+       (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
 
 #define NSEC_PER_SEC 1E9
 #define NSEC2CLK(__ns, __freq) (((__ns) * (__freq)) / NSEC_PER_SEC)
@@ -83,14 +110,11 @@
 #define timvf_read64 rte_read64_relaxed
 #define timvf_write64 rte_write64_relaxed
 
+#define TIMVF_ENABLE_STATS_ARG               ("timvf_stats")
+
 extern int otx_logtype_timvf;
 static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;
 
-struct timvf_info {
-       uint16_t domain; /* Domain id */
-       uint8_t total_timvfs; /* Total timvf available in domain */
-};
-
 enum timvf_clk_src {
        TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
        TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
@@ -115,7 +139,7 @@ struct tim_mem_bucket {
        };
        uint64_t current_chunk;
        uint64_t pad;
-} __rte_packed;
+} __rte_packed __rte_aligned(8);
 
 struct tim_mem_entry {
        uint64_t w0;
@@ -145,6 +169,7 @@ struct timvf_ring {
        struct tim_mem_bucket *bkt;
        void *chunk_pool;
        uint64_t tck_int;
+       volatile uint64_t tim_arm_cnt;
        uint64_t tck_nsec;
        void  *vbar0;
        void *bkt_pos;
@@ -160,10 +185,37 @@ bkt_mod(const uint32_t rel_bkt, const uint32_t nb_bkts)
        return rel_bkt % nb_bkts;
 }
 
-int timvf_info(struct timvf_info *tinfo);
+static __rte_always_inline uint32_t
+bkt_and(uint32_t rel_bkt, uint32_t nb_bkts)
+{
+       return rel_bkt & (nb_bkts - 1);
+}
+
+uint8_t timvf_get_ring(void);
+void timvf_release_ring(uint8_t vfid);
 void *timvf_bar(uint8_t id, uint8_t bar);
 int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,
                uint32_t *caps, const struct rte_event_timer_adapter_ops **ops,
                uint8_t enable_stats);
+uint16_t timvf_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint16_t nb_timers);
+uint16_t timvf_timer_arm_burst_sp(const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint16_t nb_timers);
+uint16_t timvf_timer_arm_burst_sp_stats(
+               const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint16_t nb_timers);
+uint16_t timvf_timer_arm_burst_mp(const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint16_t nb_timers);
+uint16_t timvf_timer_arm_burst_mp_stats(
+               const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint16_t nb_timers);
+uint16_t timvf_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint64_t timeout_tick,
+               const uint16_t nb_timers);
+uint16_t timvf_timer_arm_tmo_brst_stats(
+               const struct rte_event_timer_adapter *adptr,
+               struct rte_event_timer **tim, const uint64_t timeout_tick,
+               const uint16_t nb_timers);
+void timvf_set_chunk_refill(struct timvf_ring * const timr, uint8_t use_fpa);
 
 #endif /* __TIMVF_EVDEV_H__ */