#include <rte_bus_pci.h>
#include <rte_common.h>
#include <rte_eal.h>
-#include <rte_eventdev_pmd_pci.h>
+#include <eventdev_pmd_pci.h>
#include <rte_kvargs.h>
#include <rte_mbuf_pool_ops.h>
#include <rte_pci.h>
-#include "otx2_evdev_stats.h"
#include "otx2_evdev.h"
+#include "otx2_evdev_crypto_adptr_tx.h"
+#include "otx2_evdev_stats.h"
#include "otx2_irq.h"
#include "otx2_tim_evdev.h"
};
/* Tx modes */
- const event_tx_adapter_enqueue
+ const event_tx_adapter_enqueue_t
ssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = \
otx2_ssogws_tx_adptr_enq_ ## name,
-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
+ SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
#undef T
- };
+ };
- const event_tx_adapter_enqueue
+ const event_tx_adapter_enqueue_t
ssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = \
otx2_ssogws_tx_adptr_enq_seg_ ## name,
-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
+ SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
#undef T
- };
+ };
- const event_tx_adapter_enqueue
+ const event_tx_adapter_enqueue_t
ssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = \
otx2_ssogws_dual_tx_adptr_enq_ ## name,
-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
+ SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
#undef T
- };
+ };
- const event_tx_adapter_enqueue
+ const event_tx_adapter_enqueue_t
ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = \
otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
+ SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
#undef T
- };
+ };
event_dev->enqueue = otx2_ssogws_enq;
event_dev->enqueue_burst = otx2_ssogws_enq_burst;
[!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
[!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
}
+ event_dev->ca_enqueue = otx2_ssogws_ca_enq;
if (dev->dual_ws) {
event_dev->enqueue = otx2_ssogws_dual_enq;
[!!(dev->tx_offloads &
NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
}
+ event_dev->ca_enqueue = otx2_ssogws_dual_ca_enq;
}
event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
ws->port = i;
base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
+ ws->base[0] = base;
vws++;
base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
+ ws->base[1] = base;
vws++;
gws_cookie = ssogws_get_cookie(ws);
struct otx2_ssogws *ws;
uintptr_t base;
- /* Free memory prior to re-allocation if needed */
if (event_dev->data->ports[i] != NULL) {
ws = event_dev->data->ports[i];
- rte_free(ssogws_get_cookie(ws));
- ws = NULL;
- }
+ } else {
+ /* Allocate event port memory */
+ ws = rte_zmalloc_socket("otx2_sso_ws",
+ sizeof(struct otx2_ssogws) +
+ RTE_CACHE_LINE_SIZE,
+ RTE_CACHE_LINE_SIZE,
+ event_dev->data->socket_id);
+ if (ws == NULL) {
+ otx2_err("Failed to alloc memory for port=%d",
+ i);
+ rc = -ENOMEM;
+ break;
+ }
- /* Allocate event port memory */
- ws = rte_zmalloc_socket("otx2_sso_ws",
- sizeof(struct otx2_ssogws) +
- RTE_CACHE_LINE_SIZE,
- RTE_CACHE_LINE_SIZE,
- event_dev->data->socket_id);
- if (ws == NULL) {
- otx2_err("Failed to alloc memory for port=%d", i);
- rc = -ENOMEM;
- break;
+ /* First cache line is reserved for cookie */
+ ws = (struct otx2_ssogws *)
+ ((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
}
- /* First cache line is reserved for cookie */
- ws = (struct otx2_ssogws *)
- ((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
-
ws->port = i;
base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
sso_set_port_ops(ws, base);
+ ws->base = base;
gws_cookie = ssogws_get_cookie(ws);
gws_cookie->event_dev = event_dev;
dev->fc_iova = mz->iova;
dev->fc_mem = mz->addr;
-
+ *dev->fc_mem = 0;
aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
memset(aura, 0, sizeof(struct npa_aura_s));
return otx2_mbox_process(mbox);
}
+static int
+sso_ggrp_free_xaq(struct otx2_sso_evdev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+ struct sso_release_xaq *req;
+
+ otx2_sso_dbg("Freeing XAQ for GGRPs");
+ req = otx2_mbox_alloc_msg_sso_hw_release_xaq_aura(mbox);
+ req->hwgrps = dev->nb_event_queues;
+
+ return otx2_mbox_process(mbox);
+}
+
static void
sso_lf_teardown(struct otx2_sso_evdev *dev,
enum otx2_sso_lf_type lf_type)
ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
ws->swtag_req = 0;
ws->vws = 0;
- ws->ws_state[0].cur_grp = 0;
- ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
- ws->ws_state[1].cur_grp = 0;
- ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
+ ws->fc_mem = dev->fc_mem;
+ ws->xaq_lmt = dev->xaq_lmt;
} else {
struct otx2_ssogws *ws;
ws = event_dev->data->ports[i];
ssogws_reset(ws);
ws->swtag_req = 0;
- ws->cur_grp = 0;
- ws->cur_tt = SSO_SYNC_EMPTY;
+ ws->fc_mem = dev->fc_mem;
+ ws->xaq_lmt = dev->xaq_lmt;
}
}
otx2_write64(enable, ws->grps_base[i] +
SSO_LF_GGRP_QCTL);
}
- ws->ws_state[0].cur_grp = 0;
- ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
} else {
struct otx2_ssogws *ws = event_dev->data->ports[0];
otx2_write64(enable, ws->grps_base[i] +
SSO_LF_GGRP_QCTL);
}
- ws->cur_grp = 0;
- ws->cur_tt = SSO_SYNC_EMPTY;
}
/* reset SSO GWS cache */
sso_xae_reconfigure(struct rte_eventdev *event_dev)
{
struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
- struct rte_mempool *prev_xaq_pool;
int rc = 0;
if (event_dev->data->dev_started)
sso_cleanup(event_dev, 0);
- prev_xaq_pool = dev->xaq_pool;
+ rc = sso_ggrp_free_xaq(dev);
+ if (rc < 0) {
+ otx2_err("Failed to free XAQ\n");
+ return rc;
+ }
+
+ rte_mempool_free(dev->xaq_pool);
dev->xaq_pool = NULL;
rc = sso_xaq_allocate(dev);
if (rc < 0) {
otx2_err("Failed to alloc xaq pool %d", rc);
- rte_mempool_free(prev_xaq_pool);
return rc;
}
rc = sso_ggrp_alloc_xaq(dev);
if (rc < 0) {
otx2_err("Failed to alloc xaq to ggrp %d", rc);
- rte_mempool_free(prev_xaq_pool);
return rc;
}
- rte_mempool_free(prev_xaq_pool);
rte_mb();
if (event_dev->data->dev_started)
sso_cleanup(event_dev, 1);
}
/* Initialize and register event driver with DPDK Application */
-static struct rte_eventdev_ops otx2_sso_ops = {
+static struct eventdev_ops otx2_sso_ops = {
.dev_infos_get = otx2_sso_info_get,
.dev_configure = otx2_sso_configure,
.queue_def_conf = otx2_sso_queue_def_conf,
#define OTX2_SSO_XAE_CNT "xae_cnt"
#define OTX2_SSO_SINGLE_WS "single_ws"
#define OTX2_SSO_GGRP_QOS "qos"
+#define OTX2_SSO_FORCE_BP "force_rx_bp"
static void
parse_queue_param(char *value, void *opaque)
&single_ws);
rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
dev);
+ rte_kvargs_process(kvlist, OTX2_SSO_FORCE_BP, &parse_kvargs_flag,
+ &dev->force_rx_bp);
otx2_parse_common_devargs(kvlist);
dev->dual_ws = !single_ws;
rte_kvargs_free(kvlist);
RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
OTX2_SSO_SINGLE_WS "=1"
OTX2_SSO_GGRP_QOS "=<string>"
+ OTX2_SSO_FORCE_BP "=1"
OTX2_NPA_LOCK_MASK "=<1-65535>");
git.droids-corp.org / dpdk.git / blobdiff