#include <dlfcn.h>
-#include <rte_common.h>
-#include <rte_log.h>
#include <rte_malloc.h>
-#include <rte_errno.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_byteorder.h>
#include <rte_dev.h>
#include <gpudev_driver.h>
+
#include <cuda.h>
#include <cudaTypedefs.h>
+#include "common.h"
+#include "devices.h"
+
#define CUDA_DRIVER_MIN_VERSION 11040
#define CUDA_API_MIN_VERSION 3020
static void *cudalib;
static unsigned int cuda_api_version;
static int cuda_driver_version;
-
-/* NVIDIA GPU vendor */
-#define NVIDIA_GPU_VENDOR_ID (0x10de)
-
-/* NVIDIA GPU device IDs */
-#define NVIDIA_GPU_A100_40GB_DEVICE_ID (0x20f1)
-#define NVIDIA_GPU_A100_80GB_DEVICE_ID (0x20b5)
-#define NVIDIA_GPU_A100_80GB_DPU_DEVICE_ID (0x20b8)
-
-#define NVIDIA_GPU_A30_24GB_DEVICE_ID (0x20b7)
-#define NVIDIA_GPU_A10_24GB_DEVICE_ID (0x2236)
-
-#define NVIDIA_GPU_V100_32GB_SXM_DEVICE_ID (0x1db5)
-#define NVIDIA_GPU_V100_32GB_PCIE_DEVICE_ID (0x1db6)
-#define NVIDIA_GPU_V100_16GB_DEVICE_ID (0x1db4)
-
-#define NVIDIA_GPU_T4_16GB_DEVICE_ID (0x1eb8)
+static gdr_t gdrc_h;
#define CUDA_MAX_ALLOCATION_NUM 512
#define GPU_PAGE_SHIFT 16
#define GPU_PAGE_SIZE (1UL << GPU_PAGE_SHIFT)
-static RTE_LOG_REGISTER_DEFAULT(cuda_logtype, NOTICE);
-
-/* Helper macro for logging */
-#define rte_cuda_log(level, fmt, ...) \
- rte_log(RTE_LOG_ ## level, cuda_logtype, fmt "\n", ##__VA_ARGS__)
-
-#define rte_cuda_debug(fmt, ...) \
- rte_cuda_log(DEBUG, RTE_STR(__LINE__) ":%s() " fmt, __func__, \
- ##__VA_ARGS__)
+RTE_LOG_REGISTER_DEFAULT(cuda_logtype, NOTICE);
/* NVIDIA GPU address map */
static const struct rte_pci_id pci_id_cuda_map[] = {
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_A100_40GB_DEVICE_ID)
+ NVIDIA_GPU_A40_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_A100_80GB_DEVICE_ID)
+ NVIDIA_GPU_A30_24GB_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_A100_80GB_DPU_DEVICE_ID)
+ NVIDIA_GPU_A30X_24GB_DPU_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_A30_24GB_DEVICE_ID)
+ NVIDIA_GPU_A10_24GB_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_A10_24GB_DEVICE_ID)
+ NVIDIA_GPU_A10G_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_A10M_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_A100_40GB_SXM4_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_A100_40GB_PCIE_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_A100_80GB_SXM4_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_A100_80GB_PCIE_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_A100X_80GB_DPU_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_GA100_PG506_207)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_GA100_PCIE)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_GA100_PG506_217)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100_16GB_SXM2_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_V100_32GB_SXM_DEVICE_ID)
+ NVIDIA_GPU_V100_16GB_DGXS_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100_16GB_FHHL_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100_16GB_PCIE_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100_32GB_SXM2_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_V100_16GB_DEVICE_ID)
+ NVIDIA_GPU_V100_32GB_DGXS_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100_32GB_SXM3_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100_32GB_SXM3_H_DEVICE_ID)
},
{
RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
- NVIDIA_GPU_T4_16GB_DEVICE_ID)
+ NVIDIA_GPU_V100_SXM2)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_V100S_PCIE)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_TITAN_V_CEO_ED)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_GV100GL_PG500_216)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_GV100GL_PG503_216)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_TU102_TITAN_RTX)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_TU102GL_QUADRO_RTX)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_GV100_QUADRO_DEVICE_ID)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_4000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_5000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_6000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_8000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A4000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A6000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A5000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A4500)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A5500)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A2000)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_QUADRO_RTX_A2000_12GB)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_T4G)
+ },
+ {
+ RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+ NVIDIA_GPU_T4)
},
{
.device_id = 0
CUcontext ctx;
cuda_ptr_key pkey;
enum mem_type mtype;
+ gdr_mh_t mh;
struct mem_entry *prev;
struct mem_entry *next;
};
if (getenv("CUDA_PATH_L") == NULL)
snprintf(cuda_path, 1024, "%s", "libcuda.so");
else
- snprintf(cuda_path, 1024, "%s%s", getenv("CUDA_PATH_L"), "libcuda.so");
+ snprintf(cuda_path, 1024, "%s/%s", getenv("CUDA_PATH_L"), "libcuda.so");
cudalib = dlopen(cuda_path, RTLD_LAZY);
if (cudalib == NULL) {
}
dev->mpshared->info.total_memory = parent_info.total_memory;
+ dev->mpshared->info.page_size = parent_info.page_size;
+
/*
* GPU Device private info
*/
return 0;
}
+static int
+cuda_mem_cpu_map(struct rte_gpu *dev, __rte_unused size_t size, void *ptr_in, void **ptr_out)
+{
+ struct mem_entry *mem_item;
+ cuda_ptr_key hk;
+
+ if (dev == NULL)
+ return -ENODEV;
+
+ hk = get_hash_from_ptr((void *)ptr_in);
+
+ mem_item = mem_list_find_item(hk);
+ if (mem_item == NULL) {
+ rte_cuda_log(ERR, "Memory address 0x%p not found in driver memory.", ptr_in);
+ rte_errno = EPERM;
+ return -rte_errno;
+ }
+
+ if (mem_item->mtype != GPU_MEM) {
+ rte_cuda_log(ERR, "Memory address 0x%p is not GPU memory type.", ptr_in);
+ rte_errno = EPERM;
+ return -rte_errno;
+ }
+
+ if (mem_item->size != size)
+ rte_cuda_log(WARNING,
+ "Can't expose memory area with size (%zd) different from original size (%zd).",
+ size, mem_item->size);
+
+ if (gdrcopy_pin(&gdrc_h, &(mem_item->mh), (uint64_t)mem_item->ptr_d,
+ mem_item->size, &(mem_item->ptr_h))) {
+ rte_cuda_log(ERR, "Error exposing GPU memory address 0x%p.", ptr_in);
+ rte_errno = EPERM;
+ return -rte_errno;
+ }
+
+ *ptr_out = mem_item->ptr_h;
+
+ return 0;
+}
+
static int
cuda_mem_free(struct rte_gpu *dev, void *ptr)
{
return -rte_errno;
}
+static int
+cuda_mem_cpu_unmap(struct rte_gpu *dev, void *ptr_in)
+{
+ struct mem_entry *mem_item;
+ cuda_ptr_key hk;
+
+ if (dev == NULL)
+ return -ENODEV;
+
+ hk = get_hash_from_ptr((void *)ptr_in);
+
+ mem_item = mem_list_find_item(hk);
+ if (mem_item == NULL) {
+ rte_cuda_log(ERR, "Memory address 0x%p not found in driver memory.", ptr_in);
+ rte_errno = EPERM;
+ return -rte_errno;
+ }
+
+ if (gdrcopy_unpin(gdrc_h, mem_item->mh, (void *)mem_item->ptr_d,
+ mem_item->size)) {
+ rte_cuda_log(ERR, "Error unexposing GPU memory address 0x%p.", ptr_in);
+ rte_errno = EPERM;
+ return -rte_errno;
+ }
+
+ return 0;
+}
+
static int
cuda_dev_close(struct rte_gpu *dev)
{
rte_errno = ENOTSUP;
return -rte_errno;
}
+
+ gdrc_h = NULL;
}
/* Fill HW specific part of device structure */
return -rte_errno;
}
+ dev->mpshared->info.page_size = (size_t)GPU_PAGE_SIZE;
+
/*
* GPU Device private info
*/
dev->ops.mem_free = cuda_mem_free;
dev->ops.mem_register = cuda_mem_register;
dev->ops.mem_unregister = cuda_mem_unregister;
- dev->ops.mem_cpu_map = NULL;
- dev->ops.mem_cpu_unmap = NULL;
+ dev->ops.mem_cpu_map = cuda_mem_cpu_map;
+ dev->ops.mem_cpu_unmap = cuda_mem_cpu_unmap;
dev->ops.wmb = cuda_wmb;
rte_gpu_complete_new(dev);
git.droids-corp.org / dpdk.git / blobdiff