common/mlx5: fix default devargs initialization

[dpdk.git] / drivers / gpu / cuda / cuda.c

diff --git a/drivers/gpu/cuda/cuda.c b/drivers/gpu/cuda/cuda.c
index 408b659..efb5d14 100644 (file)
--- a/drivers/gpu/cuda/cuda.c
+++ b/drivers/gpu/cuda/cuda.c
@@ -4,19 +4,19 @@
 
 #include <dlfcn.h>
 
-#include <rte_common.h>
-#include <rte_log.h>
 #include <rte_malloc.h>
-#include <rte_errno.h>
 #include <rte_pci.h>
 #include <rte_bus_pci.h>
 #include <rte_byteorder.h>
 #include <rte_dev.h>
 
 #include <gpudev_driver.h>
+
 #include <cuda.h>
 #include <cudaTypedefs.h>
 
+#include "common.h"
+
 #define CUDA_DRIVER_MIN_VERSION 11040
 #define CUDA_API_MIN_VERSION 3020
 
@@ -51,6 +51,7 @@ static PFN_cuFlushGPUDirectRDMAWrites pfn_cuFlushGPUDirectRDMAWrites;
 static void *cudalib;
 static unsigned int cuda_api_version;
 static int cuda_driver_version;
+static gdr_t gdrc_h;
 
 /* NVIDIA GPU vendor */
 #define NVIDIA_GPU_VENDOR_ID (0x10de)
@@ -63,7 +64,8 @@ static int cuda_driver_version;
 #define NVIDIA_GPU_A30_24GB_DEVICE_ID (0x20b7)
 #define NVIDIA_GPU_A10_24GB_DEVICE_ID (0x2236)
 
-#define NVIDIA_GPU_V100_32GB_DEVICE_ID (0x1db6)
+#define NVIDIA_GPU_V100_32GB_SXM_DEVICE_ID (0x1db5)
+#define NVIDIA_GPU_V100_32GB_PCIE_DEVICE_ID (0x1db6)
 #define NVIDIA_GPU_V100_16GB_DEVICE_ID (0x1db4)
 
 #define NVIDIA_GPU_T4_16GB_DEVICE_ID (0x1eb8)
@@ -73,15 +75,7 @@ static int cuda_driver_version;
 #define GPU_PAGE_SHIFT 16
 #define GPU_PAGE_SIZE (1UL << GPU_PAGE_SHIFT)
 
-static RTE_LOG_REGISTER_DEFAULT(cuda_logtype, NOTICE);
-
-/* Helper macro for logging */
-#define rte_cuda_log(level, fmt, ...) \
-       rte_log(RTE_LOG_ ## level, cuda_logtype, fmt "\n", ##__VA_ARGS__)
-
-#define rte_cuda_debug(fmt, ...) \
-       rte_cuda_log(DEBUG, RTE_STR(__LINE__) ":%s() " fmt, __func__, \
-               ##__VA_ARGS__)
+RTE_LOG_REGISTER_DEFAULT(cuda_logtype, NOTICE);
 
 /* NVIDIA GPU address map */
 static const struct rte_pci_id pci_id_cuda_map[] = {
@@ -107,7 +101,11 @@ static const struct rte_pci_id pci_id_cuda_map[] = {
        },
        {
                RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
-                               NVIDIA_GPU_V100_32GB_DEVICE_ID)
+                               NVIDIA_GPU_V100_32GB_SXM_DEVICE_ID)
+       },
+       {
+               RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
+                               NVIDIA_GPU_V100_32GB_PCIE_DEVICE_ID)
        },
        {
                RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID,
@@ -152,6 +150,7 @@ struct mem_entry {
        CUcontext ctx;
        cuda_ptr_key pkey;
        enum mem_type mtype;
+       gdr_mh_t mh;
        struct mem_entry *prev;
        struct mem_entry *next;
 };
@@ -792,6 +791,47 @@ cuda_mem_register(struct rte_gpu *dev, size_t size, void *ptr)
        return 0;
 }
 
+static int
+cuda_mem_cpu_map(struct rte_gpu *dev, __rte_unused size_t size, void *ptr_in, void **ptr_out)
+{
+       struct mem_entry *mem_item;
+       cuda_ptr_key hk;
+
+       if (dev == NULL)
+               return -ENODEV;
+
+       hk = get_hash_from_ptr((void *)ptr_in);
+
+       mem_item = mem_list_find_item(hk);
+       if (mem_item == NULL) {
+               rte_cuda_log(ERR, "Memory address 0x%p not found in driver memory.", ptr_in);
+               rte_errno = EPERM;
+               return -rte_errno;
+       }
+
+       if (mem_item->mtype != GPU_MEM) {
+               rte_cuda_log(ERR, "Memory address 0x%p is not GPU memory type.", ptr_in);
+               rte_errno = EPERM;
+               return -rte_errno;
+       }
+
+       if (mem_item->size != size)
+               rte_cuda_log(WARNING,
+                               "Can't expose memory area with size (%zd) different from original size (%zd).",
+                               size, mem_item->size);
+
+       if (gdrcopy_pin(&gdrc_h, &(mem_item->mh), (uint64_t)mem_item->ptr_d,
+                                       mem_item->size, &(mem_item->ptr_h))) {
+               rte_cuda_log(ERR, "Error exposing GPU memory address 0x%p.", ptr_in);
+               rte_errno = EPERM;
+               return -rte_errno;
+       }
+
+       *ptr_out = mem_item->ptr_h;
+
+       return 0;
+}
+
 static int
 cuda_mem_free(struct rte_gpu *dev, void *ptr)
 {
@@ -869,6 +909,34 @@ cuda_mem_unregister(struct rte_gpu *dev, void *ptr)
        return -rte_errno;
 }
 
+static int
+cuda_mem_cpu_unmap(struct rte_gpu *dev, void *ptr_in)
+{
+       struct mem_entry *mem_item;
+       cuda_ptr_key hk;
+
+       if (dev == NULL)
+               return -ENODEV;
+
+       hk = get_hash_from_ptr((void *)ptr_in);
+
+       mem_item = mem_list_find_item(hk);
+       if (mem_item == NULL) {
+               rte_cuda_log(ERR, "Memory address 0x%p not found in driver memory.", ptr_in);
+               rte_errno = EPERM;
+               return -rte_errno;
+       }
+
+       if (gdrcopy_unpin(gdrc_h, mem_item->mh, (void *)mem_item->ptr_d,
+                       mem_item->size)) {
+               rte_cuda_log(ERR, "Error unexposing GPU memory address 0x%p.", ptr_in);
+               rte_errno = EPERM;
+               return -rte_errno;
+       }
+
+       return 0;
+}
+
 static int
 cuda_dev_close(struct rte_gpu *dev)
 {
@@ -1035,6 +1103,8 @@ cuda_gpu_probe(__rte_unused struct rte_pci_driver *pci_drv, struct rte_pci_devic
                        rte_errno = ENOTSUP;
                        return -rte_errno;
                }
+
+               gdrc_h = NULL;
        }
 
        /* Fill HW specific part of device structure */
@@ -1177,8 +1247,8 @@ cuda_gpu_probe(__rte_unused struct rte_pci_driver *pci_drv, struct rte_pci_devic
        dev->ops.mem_free = cuda_mem_free;
        dev->ops.mem_register = cuda_mem_register;
        dev->ops.mem_unregister = cuda_mem_unregister;
-       dev->ops.mem_cpu_map = NULL;
-       dev->ops.mem_cpu_unmap = NULL;
+       dev->ops.mem_cpu_map = cuda_mem_cpu_map;
+       dev->ops.mem_cpu_unmap = cuda_mem_cpu_unmap;
        dev->ops.wmb = cuda_wmb;
 
        rte_gpu_complete_new(dev);