net/cnxk: disable default inner checksum for outbound inline

[dpdk.git] / drivers / mempool / cnxk / cnxk_mempool.c

diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c
index a48b6b9..ea47355 100644 (file)
--- a/drivers/mempool/cnxk/cnxk_mempool.c
+++ b/drivers/mempool/cnxk/cnxk_mempool.c
@@ -65,6 +65,13 @@ exit:
        return max_pools;
 }
 
+static int
+cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev)
+{
+       roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs));
+       return 0;
+}
+
 static inline char *
 npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)
 {
@@ -92,7 +99,6 @@ npa_init(struct rte_pci_device *pci_dev)
        dev = mz->addr;
        dev->pci_dev = pci_dev;
 
-       roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs));
        rc = roc_npa_dev_init(dev);
        if (rc)
                goto mz_free;
@@ -155,48 +161,20 @@ npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 }
 
 static const struct rte_pci_id npa_pci_map[] = {
-       {
-               .class_id = RTE_CLASS_ANY_ID,
-               .vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
-               .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KA,
-       },
-       {
-               .class_id = RTE_CLASS_ANY_ID,
-               .vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
-               .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,
-       },
-       {
-               .class_id = RTE_CLASS_ANY_ID,
-               .vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
-               .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,
-       },
-       {
-               .class_id = RTE_CLASS_ANY_ID,
-               .vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
-               .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KA,
-       },
-       {
-               .class_id = RTE_CLASS_ANY_ID,
-               .vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
-               .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,
-       },
-       {
-               .class_id = RTE_CLASS_ANY_ID,
-               .vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
-               .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
-               .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,
-       },
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_PF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_VF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_VF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_VF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_VF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_VF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_NPA_VF),
+       CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_VF),
        {
                .vendor_id = 0,
        },
@@ -214,3 +192,8 @@ RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map);
 RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci");
 RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk,
                              CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>");
+
+RTE_INIT(cnxk_mempool_parse_devargs)
+{
+       roc_npa_lf_init_cb_register(cnxk_mempool_plt_parse_devargs);
+}