mempool/octeontx: fix build with old gcc

[dpdk.git] / drivers / mempool / octeontx / octeontx_fpavf.h

diff --git a/drivers/mempool/octeontx/octeontx_fpavf.h b/drivers/mempool/octeontx/octeontx_fpavf.h
index 5c4ee04..7a39cd2 100644 (file)
--- a/drivers/mempool/octeontx/octeontx_fpavf.h
+++ b/drivers/mempool/octeontx/octeontx_fpavf.h
@@ -33,11 +33,32 @@
 #ifndef        __OCTEONTX_FPAVF_H__
 #define        __OCTEONTX_FPAVF_H__
 
+#include <rte_debug.h>
+#include <rte_io.h>
+
+#ifdef RTE_LIBRTE_OCTEONTX_MEMPOOL_DEBUG
+#define fpavf_log_info(fmt, args...) \
+       RTE_LOG(INFO, PMD, "%s() line %u: " fmt "\n", \
+               __func__, __LINE__, ## args)
+#define fpavf_log_dbg(fmt, args...) \
+       RTE_LOG(DEBUG, PMD, "%s() line %u: " fmt "\n", \
+               __func__, __LINE__, ## args)
+#else
+#define fpavf_log_info(fmt, args...)
+#define fpavf_log_dbg(fmt, args...)
+#endif
+
+#define fpavf_func_trace fpavf_log_dbg
+#define fpavf_log_err(fmt, args...) \
+       RTE_LOG(ERR, PMD, "%s() line %u: " fmt "\n", \
+               __func__, __LINE__, ## args)
+
 /* fpa pool Vendor ID and Device ID */
 #define PCI_VENDOR_ID_CAVIUM           0x177D
 #define PCI_DEVICE_ID_OCTEONTX_FPA_VF  0xA053
 
 #define        FPA_VF_MAX                      32
+#define FPA_GPOOL_MASK                 (FPA_VF_MAX-1)
 
 /* FPA VF register offsets */
 #define FPA_VF_INT(x)                  (0x200ULL | ((x) << 22))
@@ -68,4 +89,60 @@
 #define        FPA_VF0_APERTURE_SHIFT          22
 #define FPA_AURA_SET_SIZE              16
 
+#define FPA_MAX_OBJ_SIZE               (128 * 1024)
+#define OCTEONTX_FPAVF_BUF_OFFSET      128
+
+/*
+ * In Cavium OcteonTX SoC, all accesses to the device registers are
+ * implicitly strongly ordered. So, the relaxed version of IO operation is
+ * safe to use with out any IO memory barriers.
+ */
+#define fpavf_read64 rte_read64_relaxed
+#define fpavf_write64 rte_write64_relaxed
+
+/* ARM64 specific functions */
+#if defined(RTE_ARCH_ARM64)
+#define fpavf_load_pair(val0, val1, addr) ({           \
+                       asm volatile(                   \
+                       "ldp %x[x0], %x[x1], [%x[p1]]"  \
+                       :[x0]"=r"(val0), [x1]"=r"(val1) \
+                       :[p1]"r"(addr)                  \
+                       ); })
+
+#define fpavf_store_pair(val0, val1, addr) ({          \
+                       asm volatile(                   \
+                       "stp %x[x0], %x[x1], [%x[p1]]"  \
+                       ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
+                       ); })
+#else /* Un optimized functions for building on non arm64 arch */
+
+#define fpavf_load_pair(val0, val1, addr)              \
+do {                                                   \
+       val0 = rte_read64(addr);                        \
+       val1 = rte_read64(((uint8_t *)addr) + 8);       \
+} while (0)
+
+#define fpavf_store_pair(val0, val1, addr)             \
+do {                                                   \
+       rte_write64(val0, addr);                        \
+       rte_write64(val1, (((uint8_t *)addr) + 8));     \
+} while (0)
+#endif
+
+uintptr_t
+octeontx_fpa_bufpool_create(unsigned int object_size, unsigned int object_count,
+                               unsigned int buf_offset, char **va_start,
+                               int node);
+int
+octeontx_fpa_bufpool_destroy(uintptr_t handle, int node);
+int
+octeontx_fpa_bufpool_block_size(uintptr_t handle);
+int
+octeontx_fpa_bufpool_free_count(uintptr_t handle);
+
+static __rte_always_inline uint8_t
+octeontx_fpa_bufpool_gpool(uintptr_t handle)
+{
+       return (uint8_t)handle & FPA_GPOOL_MASK;
+}
 #endif /* __OCTEONTX_FPAVF_H__ */