/* separate cache line */
/* second cache line - fields only used in slow path */
- MARKER cacheline1 __rte_cache_min_aligned;
+ RTE_MARKER cacheline1 __rte_cache_min_aligned;
volatile uint32_t prod_index; /* step 2 filled by FPGA */
} __rte_cache_aligned;
uint32_t i;
int status;
- /* Future works: divide the Q's evenly with multi-ports */
- int port = dev->data->port_id;
- int qidx = port + queue_idx;
+ int qidx = queue_idx;
/* We may already be setup, free memory prior to re-allocation */
if (dev->data->rx_queues[queue_idx] != NULL) {