* there is minimal documentation.
*/
-/* Meta data structure apssed from FPGA, must match layout in FPGA */
+/* Meta data structure passed from FPGA, must match layout in FPGA
+ * -- 32 bytes
+ */
struct ark_rx_meta {
- uint64_t timestamp;
- uint64_t user_data;
- uint8_t port;
- uint8_t dst_queue;
+ uint32_t user_meta[5]; /* user defined based on fpga code */
+ uint8_t reserved[10];
uint16_t pkt_len;
-};
+} __rte_packed;
/*
* UDM hardware structures
#define ARK_RX_WRITE_TIME_NS 2500
#define ARK_UDM_SETUP 0
-#define ARK_UDM_CONST 0xbACECACE
+#define ARK_UDM_CONST2 0xbACECACE
+#define ARK_UDM_CONST3 0x344d4455
+#define ARK_UDM_CONST ARK_UDM_CONST3
struct ark_udm_setup_t {
uint32_t r0;
uint32_t r4;