net/axgbe: use common bit operations API

[dpdk.git] / drivers / net / axgbe / axgbe_common.h

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 97a80f5..d53b48c 100644 (file)
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -21,6 +21,7 @@
 #include <inttypes.h>
 #include <pthread.h>
 
+#include <rte_bitops.h>
 #include <rte_byteorder.h>
 #include <rte_memory.h>
 #include <rte_malloc.h>
@@ -34,7 +35,6 @@
 #include <rte_ethdev.h>
 #include <rte_dev.h>
 #include <rte_errno.h>
-#include <rte_dev.h>
 #include <rte_ethdev_pci.h>
 #include <rte_common.h>
 #include <rte_cycles.h>
@@ -290,6 +290,11 @@
 #define MAC_RQC2_INC                   4
 #define MAC_RQC2_Q_PER_REG             4
 
+#define MAC_MACAHR(i)  (MAC_MACA0HR + ((i) * 8))
+#define MAC_MACALR(i)  (MAC_MACA0LR + ((i) * 8))
+
+#define MAC_HTR(i)     (MAC_HTR0 + ((i) * MAC_HTR_INC))
+
 /* MAC register entry bit positions and sizes */
 #define MAC_HWF0R_ADDMACADRSEL_INDEX   18
 #define MAC_HWF0R_ADDMACADRSEL_WIDTH   5
@@ -833,6 +838,22 @@
 #define MTL_TC_ETSCR_TSA_WIDTH         2
 #define MTL_TC_QWR_QW_INDEX            0
 #define MTL_TC_QWR_QW_WIDTH            21
+#define MTL_TCPM0R_PSTC0_INDEX         0
+#define MTL_TCPM0R_PSTC0_WIDTH         8
+#define MTL_TCPM0R_PSTC1_INDEX         8
+#define MTL_TCPM0R_PSTC1_WIDTH         8
+#define MTL_TCPM0R_PSTC2_INDEX         16
+#define MTL_TCPM0R_PSTC2_WIDTH         8
+#define MTL_TCPM0R_PSTC3_INDEX         24
+#define MTL_TCPM0R_PSTC3_WIDTH         8
+#define MTL_TCPM1R_PSTC4_INDEX         0
+#define MTL_TCPM1R_PSTC4_WIDTH         8
+#define MTL_TCPM1R_PSTC5_INDEX         8
+#define MTL_TCPM1R_PSTC5_WIDTH         8
+#define MTL_TCPM1R_PSTC6_INDEX         16
+#define MTL_TCPM1R_PSTC6_WIDTH         8
+#define MTL_TCPM1R_PSTC7_INDEX         24
+#define MTL_TCPM1R_PSTC7_WIDTH         8
 
 /* MTL traffic class register value */
 #define MTL_TSA_SP                     0x00
@@ -842,6 +863,8 @@
 #define PCS_V1_WINDOW_SELECT           0x03fc
 #define PCS_V2_WINDOW_DEF              0x9060
 #define PCS_V2_WINDOW_SELECT           0x9064
+#define PCS_V2_RV_WINDOW_DEF           0x1060
+#define PCS_V2_RV_WINDOW_SELECT                0x1064
 
 /* PCS register entry bit positions and sizes */
 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
@@ -1134,6 +1157,8 @@
 #define RX_NORMAL_DESC3_PL_WIDTH               14
 #define RX_NORMAL_DESC3_RSV_INDEX              26
 #define RX_NORMAL_DESC3_RSV_WIDTH              1
+#define RX_NORMAL_DESC3_LD_INDEX               28
+#define RX_NORMAL_DESC3_LD_WIDTH               1
 
 #define RX_DESC3_L34T_IPV4_TCP                 1
 #define RX_DESC3_L34T_IPV4_UDP                 2
@@ -1297,6 +1322,7 @@
 #define AXGBE_AN_CL37_PCS_MODE_BASEX   0x00
 #define AXGBE_AN_CL37_PCS_MODE_SGMII   0x04
 #define AXGBE_AN_CL37_TX_CONFIG_MASK   0x08
+#define AXGBE_AN_CL37_MII_CTRL_8BIT     0x0100
 
 #define AXGBE_PMA_CDR_TRACK_EN_MASK    0x01
 #define AXGBE_PMA_CDR_TRACK_EN_OFF     0x00
@@ -1352,9 +1378,9 @@ do {                                                                      \
 
 #define SET_BITS_LE(_var, _index, _width, _val)                                \
 do {                                                                   \
-       (_var) &= rte_cpu_to_le_32(~(((0x1 << (_width)) - 1) << (_index)));\
+       (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\
        (_var) |= rte_cpu_to_le_32((((_val) &                           \
-                             ((0x1 << (_width)) - 1)) << (_index)));   \
+                             ((0x1U << (_width)) - 1)) << (_index)));  \
 } while (0)
 
 /* Bit setting and getting macros based on register fields
@@ -1675,34 +1701,6 @@ do {                                                                     \
 #define time_after_eq(a, b)     ((long)((a) - (b)) >= 0)
 #define time_before_eq(a, b)   time_after_eq(b, a)
 
-/*---bitmap support apis---*/
-static inline int axgbe_test_bit(int nr, volatile unsigned long *addr)
-{
-       int res;
-
-       rte_mb();
-       res = ((*addr) & (1UL << nr)) != 0;
-       rte_mb();
-       return res;
-}
-
-static inline void axgbe_set_bit(unsigned int nr, volatile unsigned long *addr)
-{
-       __sync_fetch_and_or(addr, (1UL << nr));
-}
-
-static inline void axgbe_clear_bit(int nr, volatile unsigned long *addr)
-{
-       __sync_fetch_and_and(addr, ~(1UL << nr));
-}
-
-static inline int axgbe_test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-       unsigned long mask = (1UL << nr);
-
-       return __sync_fetch_and_and(addr, ~mask) & mask;
-}
-
 static inline unsigned long msecs_to_timer_cycles(unsigned int m)
 {
        return rte_get_timer_hz() * (m / 1000);