#endif
#define AXGBE_HZ 250
+#define NSEC_PER_SEC 1000000000L
/* DMA register offsets */
#define DMA_MR 0x3000
#define MAC_TSCR_TSEVNTENA_WIDTH 1
#define MAC_TSCR_TSINIT_INDEX 2
#define MAC_TSCR_TSINIT_WIDTH 1
+#define MAC_TSCR_TSUPDT_INDEX 3
+#define MAC_TSCR_TSUPDT_WIDTH 1
#define MAC_TSCR_TSIPENA_INDEX 11
#define MAC_TSCR_TSIPENA_WIDTH 1
#define MAC_TSCR_TSIPV4ENA_INDEX 13
#define MAC_TSCR_TXTSSTSM_WIDTH 1
#define MAC_TSSR_TXTSC_INDEX 15
#define MAC_TSSR_TXTSC_WIDTH 1
+#define MAC_STNUR_ADDSUB_INDEX 31
+#define MAC_STNUR_ADDSUB_WIDTH 1
#define MAC_TXSNR_TXTSSTSMIS_INDEX 31
#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
#define MAC_VLANHTR_VLHT_INDEX 0
#define MAC_VR_USERVER_INDEX 16
#define MAC_VR_USERVER_WIDTH 8
+
/* MMC register offsets */
#define MMC_CR 0x0800
#define MMC_RISR 0x0804
#define RX_CONTEXT_DESC3_TSA_WIDTH 1
#define RX_CONTEXT_DESC3_TSD_INDEX 6
#define RX_CONTEXT_DESC3_TSD_WIDTH 1
+#define RX_CONTEXT_DESC3_PMT_INDEX 0
+#define RX_CONTEXT_DESC3_PMT_WIDTH 4
#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1